Hi all,
I have tried the deep sleep mode of dm365 by lowering the GIO 0 low and setting the 31st bit in DEEPSLEEP register.I am following the below sequence to enter into Deep Sleep Mode:
(1) Put DDR into self refresh (setting 31st, 30th bit and clearing 23rd bit of SDRCR register).
(2) Setting the 6th and 8th bit of VTP register.
(3) Power down USB PHY (USB_PHY_CTRL register), disabling VDAC, VPSS and EMIF modules through PSC controller.
(4) Power down PLL2
(5) Power down PLL1
(6) Go sleep mode
The processor wakes up whenever there is a low to high transition on GIO 0. (This is observed by increase of current consumption)
(1) Turn on PLL1
(2) Turn on PLL2
(3) Enable DDR, USB PHY, VPSS and VDAC
(4) Enable DDR clock by clearing the 30th bit of SDRCR register in DDR controller and waiting for PHYRDY to set in SDRSTAT.
(5) Bring DDR out off self-refresh by clearing 31st bit of SDRCR.
My
code is running from internal ARM RAM and once it ends after bringing
back the DDR out of self refresh it jumps back to DDR memory and
console promt becomes active.
The problem I am facing is that once DDR comes out of self refresh
it doesnt give back the console and it looks as if the processor is
hanged. The only possibility I feel is that DDR has lost its data when
the processor went into deep sleep.
But accodring to manual this should not happen as the DDR is in
self refresh mode (not in power down mode) so its VCLK and X2_CLK can
be switched off.
Do i need to disable anything else also before
I go to Deep Sleep Mode and powering down of USB PHY, VPSS and VDAC is
necessary??? Also I want to know the correct settings of VTP register before and after deep sleep mode.
Thanks
Faraz.