Tool/software: Linux
Hi All,
There's a problem I haven't solved in a long time.
I tried to explain problem. I need your help.
Processor SDK version 05.03.00.07
We selected "AM437x Evaluation Module" as a reference designs for RAM-DDR layout.
But we used different RAM (MT41K256M16TW-107:P) on our custom board.
I created bootable SD Card with "am437x-evm-linux-05.03.00.07.img"
Boot mode pins are selected as a MMC0 first.
For initial test,we used GEL Files.
I modified "evmam437x.gel" file because of RAM difference. (I changed SDRAM data bus width from 32 to 16. --> GP_EVM_DDR3_SDRAM_CONFIG 0x61A053B2. )
Then i connected to the target and initialized board with "AM43xx_GP_EVM_Initialization" script.
All tests passed successfully. DDR works fine. I can write DDR and read DDR.
After initialization with GEL file, I did not terminate debug window, i loaded "u-boot.bin" to 0x80800000 and resume.
Log messages seen at serial port. I stopped autoboot and programmed EEPROM. I wrote board name "AM43__GP"
After these steps, Linux started successfully.
But normally, we don't want to use GEL File for initialization so i started to modify u-boot source code.
I tried to fill "SPRAC70A_AM437x_EMIF_Configuration_Tool_V21"
When i fill "SPRAC70A_AM437x_EMIF_Configuration_Tool_V21" , i inspired by "evmam437x.gel" and MT41K256M16TW Datasheet
I modified u-boot source code(board.c) according to spreadsheet.(spreadsheet and board.c are attached.)
But following register values could not change.
Because when i change this register values, i cannot see SPL log messages on serial port. So i did not change these register values.
EMIF4D_DDR_PHY_CTRL_1
EMIF4D_EXT_PHY_CTRL_1
EMIF4D_EXT_PHY_CTRL_2
EMIF4D_EXT_PHY_CTRL_3
EMIF4D_EXT_PHY_CTRL_4
EMIF4D_EXT_PHY_CTRL_5
After modifications, i built "am43xx_evm_config", "u-boot.bin" and "u-boot-spl.bin"
I followed "training.ti.com/linux-board-porting-series-module-7-debugging-u-boot-jtag-ccs for making Linux work.
I launched selected configuration and connected target.
"u-boot-spl.bin" is loaded to Memory 0x402F4000
Program Counter is set to 0x402F4000.
When i resumed, SPL log messages appeared on serial port! ( as in training module 18:35 training.ti.com/linux-board-porting-series-module-7-debugging-u-boot-jtag-ccs
/*//**/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
U-Boot SPL 2018.01-00569-gf9c38b91a2-dirty (Jun 13 2019 - 11:08:02)
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
/*//**/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/
I think everything is fine so far.
Then i loaded u-boot.bin 0x80800000
Program Counter is set to 0x80800000.
When i resumed program, i think i will see u-boot log messages ( as in training module 21:18 training.ti.com/linux-board-porting-series-module-7-debugging-u-boot-jtag-ccs
But there is nothing on serial port!
Program Counter stops at 0x402f4040.
I can't solve this problem for a long time.
When trying to solve this problem, i saw thread about Debug Server Scripting (DSS) .
"am43xx-ddr-analysis" results is also attached.
Maybe it will help us solve the problem.
I need your help.
Thanks,
Best regards,
Mehmet.
CONTROL: device_id = 0x2b98c02f
* AM43xx family
* Silicon Revision 1.2
CONTROL: control_status = 0x00400318
* Bit 26 (SYSBOOT18=0): Do not route EXTCLK to CLKOUT2
* Bits 23:22 (SYSBOOT15:14=1): 24 MHz
CM_CLKSEL_DPLL_DDR = 0x00003202
* DPLL_MULT = 50 (x50)
* DPLL_DIV = 2 (/3)
CM_DIV_M2_DPLL_DDR = 0x00000221
* CLKST = 1: M2 output clock enabled
* DIVHS = 1 (/1)
CM_DIV_M4_DPLL_DDR = 0x00000222
* CLKST = 1: M4 output clock enabled
* DIVHS = 2 (/2)
DPLL_DDR Summary
-> F_input = 24 MHz
-> CLKOUT_M2 = DDR_PLL_CLKOUT = 400 MHz
-> CLKOUT_M4 = DLL_CLKOUT = 400 MHz
EMIF: SDRAM_CONFIG = 0x638413b2
* SDRAM_TYPE = DDR3
* Bits 26:24 (reg_ddr_term) set for RZQ/6 (011b)
* Bits 19:18 (reg_sdram_drive) set for RZQ/7 (01b)
* Bits 17:16 (cwl) set for 5 (00b)
* NARROW_MODE=0 (32-bit wide)
* Bits 13:10 (CL) set for 6
* Bits 9:7 (ROWSIZE) set for 16 row bits
* Bits 6:4 (IBANK) set for 8 banks
* Bit 3 (EBANK) set for 1 chip select (CS0)
* Bits 3:0 (PAGESIZE) set for 10 column bits
EMIF: PWR_MGMT_CTRL = 0x000000a0
DDR PHY: DDR_PHY_CTRL_1 = 0x0e004008
* RDLVL_MASK=1, read leveling is disabled! Not recommended.
* RDLVLGATE_MASK=1, read leveling is disabled! Not recommended.
* WRLVL_MASK=1, write leveling is disabled! Not recommended.
* PHY_INVERT_CLKOUT=0.
* PHY_DLL_LOCK_DIFF is not set to the required value.
* READ_LAT=8, (corresponds correctly with CL and PHY_INVERT_CLKOUT)
DDR PHY: EXT_PHY_CTRL_1 = 0x08020080
DDR PHY: EXT_PHY_CTRL_36 = 0x000001ff
* Bits 7:0 recommended value is 0x77.
* Please verify you are using the latest AM43xx DDR Spreadsheet: http://www.ti.com/lit/zip/sprac70
CTRL_DDR_ADDRCTRL_IOCTRL = 0x00000084
* Bits 9:5 control ddr_ck and ddr_ckn
- Slew fastest
- Drive Strength 9 mA
* Bits 4:0 control all other address/control pins
- Slew fastest
- Drive Strength 9 mA
CTRL_DDR_ADDRCTRL_WD0_IOCTRL = 0x00000000
CTRL_DDR_ADDRCTRL_WD1_IOCTRL = 0x00000000
* [ddr_a0 ] Pullup/Pulldown disabled
* [ddr_a1 ] Pullup/Pulldown disabled
* [ddr_a2 ] Pullup/Pulldown disabled
* [ddr_a3 ] Pullup/Pulldown disabled
* [ddr_a4 ] Pullup/Pulldown disabled
* [ddr_a5 ] Pullup/Pulldown disabled
* [ddr_a6 ] Pullup/Pulldown disabled
* [ddr_a7 ] Pullup/Pulldown disabled
* [ddr_a8 ] Pullup/Pulldown disabled
* [ddr_a9 ] Pullup/Pulldown disabled
* [ddr_a10 ] Pullup/Pulldown disabled
* [ddr_a11 ] Pullup/Pulldown disabled
* [ddr_a12 ] Pullup/Pulldown disabled
* [ddr_a13 ] Pullup/Pulldown disabled
* [ddr_a14 ] Pullup/Pulldown disabled
* [ddr_a15 ] Pullup/Pulldown disabled
* [ddr_ba2 ] Pullup/Pulldown disabled
* [ddr_ba1 ] Pullup/Pulldown disabled
* [ddr_ba0 ] Pullup/Pulldown disabled
* [ddr_wen ] Pullup/Pulldown disabled
* [ddr_rasn ] Pullup/Pulldown disabled
* [ddr_casn ] Pullup/Pulldown disabled
* [ddr_nck ] Pullup/Pulldown disabled
* [ddr_ck ] Pullup/Pulldown disabled
* [ddr_cke ] Pullup/Pulldown disabled
* [ddr_csn1 ] Pullup/Pulldown disabled
* [ddr_csn0 ] Pullup/Pulldown disabled
* [ddr_resetn] Pullup/Pulldown disabled
* [ddr_odt1 ] Pullup/Pulldown disabled
* [ddr_odt0 ] Pullup/Pulldown disabled
CTRL_DDR_DATA0_IOCTRL = 0x00000084
* ddr_d0 Pullup/Pulldown disabled
* ddr_d1 Pullup/Pulldown disabled
* ddr_d2 Pullup/Pulldown disabled
* ddr_d3 Pullup/Pulldown disabled
* ddr_d4 Pullup/Pulldown disabled
* ddr_d5 Pullup/Pulldown disabled
* ddr_d6 Pullup/Pulldown disabled
* ddr_d7 Pullup/Pulldown disabled
* ddr_dqm0 Pullup/Pulldown disabled
* ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs0, ddr_dqsn0
- Slew fastest
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[7:0], dqm0
- Slew fastest
- Drive Strength 9 mA
CTRL_DDR_DATA1_IOCTRL = 0x00000084
* ddr_d8 Pullup/Pulldown disabled
* ddr_d9 Pullup/Pulldown disabled
* ddr_d10 Pullup/Pulldown disabled
* ddr_d11 Pullup/Pulldown disabled
* ddr_d12 Pullup/Pulldown disabled
* ddr_d13 Pullup/Pulldown disabled
* ddr_d14 Pullup/Pulldown disabled
* ddr_d15 Pullup/Pulldown disabled
* ddr_dqm1 Pullup/Pulldown disabled
* ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs1, ddr_dqsn1
- Slew fastest
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[15:8], ddr_dqm1
- Slew fastest
- Drive Strength 9 mA
CTRL_DDR_DATA2_IOCTRL = 0x00000084
* ddr_d16 Pullup/Pulldown disabled
* ddr_d17 Pullup/Pulldown disabled
* ddr_d18 Pullup/Pulldown disabled
* ddr_d19 Pullup/Pulldown disabled
* ddr_d20 Pullup/Pulldown disabled
* ddr_d21 Pullup/Pulldown disabled
* ddr_d22 Pullup/Pulldown disabled
* ddr_d23 Pullup/Pulldown disabled
* ddr_dqm2 Pullup/Pulldown disabled
* ddr_dqs2 and ddr_dqsn2 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs2, ddr_dqsn2
- Slew fastest
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[23:16], ddr_dqm2
- Slew fastest
- Drive Strength 9 mA
CTRL_DDR_DATA3_IOCTRL = 0x00000084
* ddr_d24 Pullup/Pulldown disabled
* ddr_d25 Pullup/Pulldown disabled
* ddr_d26 Pullup/Pulldown disabled
* ddr_d27 Pullup/Pulldown disabled
* ddr_d28 Pullup/Pulldown disabled
* ddr_d29 Pullup/Pulldown disabled
* ddr_d30 Pullup/Pulldown disabled
* ddr_d31 Pullup/Pulldown disabled
* ddr_dqm3 Pullup/Pulldown disabled
* ddr_dqs3 and ddr_dqsn3 Pullup/Pulldown disabled
* Bits 9:5 control ddr_dqs3, ddr_dqsn3
- Slew fastest
- Drive Strength 9 mA
* Bits 4:0 control ddr_d[31:24], ddr_dqm3
- Slew fastest
- Drive Strength 9 mA
CONTROL: CTRL_DDR_IO = 0x00000000
* Bit 31: DDR_RESETn controlled by EMIF.
CONTROL: CTRL_VTP = 0x00010167
* VTP not disabled (expected in normal operation, but not DS0).
CONTROL: CTRL_VREF = 0x00000000
* VREF supplied externally (typical).
CONTROL: CTRL_DDR_CKE = 0x0000000f
* CKE0 controlled by EMIF (normal/ungated operation).
* CKE1 controlled by EMIF (normal/ungated operation).
CONTROL: CTRL_EMIF_SDRAM_CONFIG_EXT = 0x0000c163
* Bit 17: NARROW_ONLY = 0
* Bits 15:14: phy_num_of_samples = 3 -> 128 samples, full leveling
* Bit 13: phy_sel_logic = 0 (Recommended)
* Bit 12: phy_all_dq_mpr_rd_resp = 0
* Bits 11:09: phy_output_sts_select = 0
* Bit 8: dynamic_pwrdn_en = 1
* Bits 06:05: phy_rd_local_odt = 3, Half Thevenin load
* Bit 3: dfi_clock_phase_ctrl = 0
* Bit 1: en_slice_1 = 1 (CMD PHY1)
* Bit 0: en_slice_0 = 1 (CMD PHY0)
/*
* board.c
*
* Board functions for TI AM43XX based boards
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <linux/errno.h>
#include <spl.h>
#include <usb.h>
#include <asm/omap_sec_common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
#include "../common/board_detect.h"
#include "board.h"
#include <power/pmic.h>
#include <power/tps65218.h>
#include <power/tps62362.h>
#include <miiphy.h>
#include <cpsw.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/*
* Read header information from EEPROM into global structure.
*/
#ifdef CONFIG_TI_I2C_BOARD_DETECT
void do_board_detect(void)
{
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS))
printf("ti_i2c_eeprom_init failed\n");
}
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
{150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
{125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
{625, 11, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 24 MHz */
{300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
{720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
{800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
{1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 25 MHz */
{300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
{720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
{800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
{1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 26 MHz */
{300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
{720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
{800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
{1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
},
};
const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
{1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
{1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
};
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
};
const struct dpll_params gp_evm_dpll_ddr = {
50, 2, 1, -1, 2, -1, -1};
static const struct dpll_params idk_dpll_ddr = {
400, 23, 1, -1, 2, -1, -1
};
static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
0x00500050,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40001000,
0x08102040
};
const struct ctrl_ioregs ioregs_lpddr2 = {
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
.cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
.dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
.dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
.dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
.dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
.emif_sdram_config_ext = 0x1,
};
const struct emif_regs emif_regs_lpddr2 = {
.sdram_config = 0x808012BA,
.ref_ctrl = 0x0000040D,
.sdram_tim1 = 0xEA86B411,
.sdram_tim2 = 0x103A094A,
.sdram_tim3 = 0x0F6BA37F,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E284006,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
.emif_ddr_ext_phy_ctrl_3 = 0x00500050,
.emif_ddr_ext_phy_ctrl_4 = 0x00500050,
.emif_ddr_ext_phy_ctrl_5 = 0x00500050,
.emif_prio_class_serv_map = 0x80000001,
.emif_connect_id_serv_1_map = 0x80000094,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x000FFFFF
};
const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
.emif_sdram_config_ext = 0xc163,
};
const struct emif_regs ddr3_emif_regs_400Mhz = {
.sdram_config = 0x61A053B2, // 0x638413B2
.ref_ctrl = 0x00000C30, // OK
.sdram_tim1 = 0xEAAAD4DB, // OK
.sdram_tim2 = 0x266B7FDA, // OK
.sdram_tim3 = 0x5F7F867F, // 0x107F8678
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50077D33, // 0x50074BE4
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
.emif_ddr_ext_phy_ctrl_4 = 0x00400040,
.emif_ddr_ext_phy_ctrl_5 = 0x00400040,
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_prio_class_serv_map = 0x80000001,
.emif_connect_id_serv_1_map = 0x80000094,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x000FFFFF
};
/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
.sdram_config = 0x638413B2,
.ref_ctrl = 0x00000C30,
.sdram_tim1 = 0xEAAAD4DB,
.sdram_tim2 = 0x266B7FDA,
.sdram_tim3 = 0x107F8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00000065,
.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
.emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
.emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_prio_class_serv_map = 0x80000001,
.emif_connect_id_serv_1_map = 0x80000094,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x000FFFFF
};
/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
const struct emif_regs ddr3_emif_regs_400Mhz_production = {
.sdram_config = 0x638413B2,
.ref_ctrl = 0x00000C30,
.sdram_tim1 = 0xEAAAD4DB,
.sdram_tim2 = 0x266B7FDA,
.sdram_tim3 = 0x107F8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E004008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00000066,
.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
.emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
.emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_prio_class_serv_map = 0x80000001,
.emif_connect_id_serv_1_map = 0x80000094,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x000FFFFF
};
static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
.sdram_config = 0x638413b2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00000c30,
.sdram_tim1 = 0xeaaad4db,
.sdram_tim2 = 0x266b7fda,
.sdram_tim3 = 0x107f8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074be4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0e084008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x89,
.emif_ddr_ext_phy_ctrl_3 = 0x90,
.emif_ddr_ext_phy_ctrl_4 = 0x8e,
.emif_ddr_ext_phy_ctrl_5 = 0x8d,
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x80000000,
.emif_prio_class_serv_map = 0x80000001,
.emif_connect_id_serv_1_map = 0x80000094,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x000FFFFF
};
static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
.sdram_config = 0x61a11b32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00000c30,
.sdram_tim1 = 0xeaaad4db,
.sdram_tim2 = 0x266b7fda,
.sdram_tim3 = 0x107f8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074be4,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1 = 0x00008009,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00000040,
.emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
.emif_ddr_ext_phy_ctrl_4 = 0x00000051,
.emif_ddr_ext_phy_ctrl_5 = 0x00000051,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000405,
.emif_prio_class_serv_map = 0x00000000,
.emif_connect_id_serv_1_map = 0x00000000,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x00ffffff
};
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
if (board_is_eposevm()) {
*regs = ext_phy_ctrl_const_base_lpddr2;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
}
return;
}
const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
else if (board_is_evm() || board_is_sk())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
printf(" Board '%s' not supported\n", board_ti_get_name());
return NULL;
}
/*
* get_opp_offset:
* Returns the index for safest OPP of the device to boot.
* max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
* min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
* This data is read from dev_attribute register which is e-fused.
* A'1' in bit indicates OPP disabled and not available, a '0' indicates
* OPP available. Lowest OPP starts with min_off. So returning the
* bit with rightmost '0'.
*/
static int get_opp_offset(int max_off, int min_off)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
int opp, offset, i;
/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
for (i = max_off; i >= min_off; i--) {
offset = opp & (1 << i);
if (!offset)
return i;
}
return min_off;
}
const struct dpll_params *get_dpll_mpu_params(void)
{
int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
u32 ind = get_sys_clk_index();
return &dpll_mpu[ind][opp];
}
const struct dpll_params *get_dpll_core_params(void)
{
int ind = get_sys_clk_index();
return &dpll_core[ind];
}
const struct dpll_params *get_dpll_per_params(void)
{
int ind = get_sys_clk_index();
return &dpll_per[ind];
}
void scale_vcores_generic(u32 m)
{
int mpu_vdd, ddr_volt;
if (i2c_probe(TPS65218_CHIP_PM))
return;
switch (m) {
case 1000:
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
break;
case 800:
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
break;
case 720:
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
break;
case 600:
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
break;
case 300:
mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
break;
default:
puts("Unknown MPU clock, not scaling\n");
return;
}
/* Set DCDC1 (CORE) voltage to 1.1V */
if (tps65218_voltage_update(TPS65218_DCDC1,
TPS65218_DCDC_VOLT_SEL_1100MV)) {
printf("%s failure\n", __func__);
return;
}
/* Set DCDC2 (MPU) voltage */
if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
printf("%s failure\n", __func__);
return;
}
if (board_is_eposevm())
ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
else
ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
/* Set DCDC3 (DDR) voltage */
if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
printf("%s failure\n", __func__);
return;
}
}
void scale_vcores_idk(u32 m)
{
int mpu_vdd;
if (i2c_probe(TPS62362_I2C_ADDR))
return;
switch (m) {
case 1000:
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
break;
case 800:
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
break;
case 720:
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
break;
case 600:
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
break;
case 300:
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
break;
default:
puts("Unknown MPU clock, not scaling\n");
return;
}
/* Set VDD_MPU voltage */
if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
printf("%s failure\n", __func__);
return;
}
}
void gpi2c_init(void)
{
/* When needed to be invoked prior to BSS initialization */
static bool first_time = true;
if (first_time) {
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
CONFIG_SYS_OMAP24_I2C_SLAVE);
first_time = false;
}
}
void scale_vcores(void)
{
const struct dpll_params *mpu_params;
/* Ensure I2C is initialized for PMIC configuration */
gpi2c_init();
/* Get the frequency */
mpu_params = get_dpll_mpu_params();
if (board_is_idk())
scale_vcores_idk(mpu_params->m);
else
scale_vcores_generic(mpu_params->m);
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
static void enable_vtt_regulator(void)
{
u32 temp;
/* enable module */
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
/* enable output for GPIO5_7 */
writel(GPIO_SETDATAOUT(7),
AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
temp = temp & ~(GPIO_OE_ENABLE(7));
writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
}
enum {
RTC_BOARD_EPOS = 1,
RTC_BOARD_EVM14,
RTC_BOARD_EVM12,
RTC_BOARD_GPEVM,
RTC_BOARD_SK,
};
/*
* In the rtc_only boot path we have the board type info in the rtc scratch pad
* register hence we bypass the costly i2c reads to eeprom and directly program
* the board name string
*/
void rtc_only_update_board_type(u32 btype)
{
const char *name = "";
const char *rev = "1.0";
switch (btype) {
case RTC_BOARD_EPOS:
name = "AM43EPOS";
break;
case RTC_BOARD_EVM14:
name = "AM43__GP";
rev = "1.4";
break;
case RTC_BOARD_EVM12:
name = "AM43__GP";
rev = "1.2";
break;
case RTC_BOARD_GPEVM:
name = "AM43__GP";
break;
case RTC_BOARD_SK:
name = "AM43__SK";
break;
}
ti_i2c_eeprom_am_set(name, rev);
}
u32 rtc_only_get_board_type(void)
{
if (board_is_eposevm())
return RTC_BOARD_EPOS;
else if (board_is_evm_14_or_later())
return RTC_BOARD_EVM14;
else if (board_is_evm_12_or_later())
return RTC_BOARD_EVM12;
else if (board_is_gpevm())
return RTC_BOARD_GPEVM;
else if (board_is_sk())
return RTC_BOARD_SK;
return 0;
}
void sdram_init(void)
{
/*
* EPOS EVM has 1GB LPDDR2 connected to EMIF.
* GP EMV has 1GB DDR3 connected to EMIF
* along with VTT regulator.
*/
if (board_is_eposevm()) {
config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
} else if (board_is_evm_14_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_production, 0);
} else if (board_is_evm_12_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
} else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
} else if (board_is_sk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_sk_emif_regs_400Mhz, 0);
} else if (board_is_idk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_idk_emif_regs_400Mhz, 0);
}
}
#endif
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
if (board_is_idk()) {
power_tps62362_init(I2C_PMIC);
p = pmic_get("TPS62362");
if (p && !pmic_probe(p))
puts("PMIC: TPS62362\n");
} else {
power_tps65218_init(I2C_PMIC);
p = pmic_get("TPS65218_PMIC");
if (p && !pmic_probe(p))
puts("PMIC: TPS65218\n");
}
return 0;
}
int board_init(void)
{
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
modena_init0_bw_integer, modena_init0_watermark_0;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
/*
* Call this to initialize ctrl again. ctrl would not have been updated
* across relocation because its address is in SRAM scratchpad
*/
hw_data_init();
/* Clear all important bits for DSS errata that may need to be tweaked*/
mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
MREQPRIO_0_SAB_INIT0_MASK;
mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
BW_LIMITER_BW_FRAC_MASK;
modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
BW_LIMITER_BW_INT_MASK;
modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
BW_LIMITER_BW_WATERMARK_MASK;
/* Setting MReq Priority of the DSS*/
mreqprio_0 |= 0x77;
/*
* Set L3 Fast Configuration Register
* Limiting bandwith for ARM core to 700 MBPS
*/
modena_init0_bw_fractional |= 0x10;
modena_init0_bw_integer |= 0x3;
writel(mreqprio_0, &cdev->mreqprio_0);
writel(mreqprio_1, &cdev->mreqprio_1);
writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info_env(NULL);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
#endif
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
.maximum_speed = USB_SPEED_HIGH,
.base = USB_OTG_SS1_BASE,
.tx_fifo_resize = false,
.index = 0,
};
static struct dwc3_omap_device usb_otg_ss1_glue = {
.base = (void *)USB_OTG_SS1_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 0,
};
static struct ti_usb_phy_device usb_phy1_device = {
.usb2_phy_power = (void *)USB2_PHY1_POWER,
.index = 0,
};
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_HIGH,
.base = USB_OTG_SS2_BASE,
.tx_fifo_resize = false,
.index = 1,
};
static struct dwc3_omap_device usb_otg_ss2_glue = {
.base = (void *)USB_OTG_SS2_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 1,
};
static struct ti_usb_phy_device usb_phy2_device = {
.usb2_phy_power = (void *)USB2_PHY2_POWER,
.index = 1,
};
int usb_gadget_handle_interrupts(int index)
{
u32 status;
status = dwc3_omap_uboot_interrupt_status(index);
if (status)
dwc3_uboot_handle_interrupt(index);
return 0;
}
#endif /* CONFIG_USB_DWC3 */
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
ti_usb_phy_uboot_init(&usb_phy1_device);
dwc3_uboot_init(&usb_otg_ss1);
}
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
ti_usb_phy_uboot_init(&usb_phy2_device);
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
dwc3_uboot_init(&usb_otg_ss2);
}
break;
default:
printf("Invalid Controller Index\n");
}
#endif
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
if (init == USB_INIT_DEVICE) {
ti_usb_phy_uboot_exit(index);
dwc3_uboot_exit(index);
dwc3_omap_uboot_exit(index);
}
break;
default:
printf("Invalid Controller Index\n");
}
#endif
disable_usb_clocks(index);
return 0;
}
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifndef CONFIG_DM_ETH
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* Additional controls can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 16,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
defined(CONFIG_SPL_USBETH_SUPPORT)) && \
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!env_get("ethaddr")) {
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
#ifndef CONFIG_SPL_BUILD
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!env_get("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("eth1addr", mac_addr);
}
#endif
if (board_is_eposevm()) {
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 16;
} else if (board_is_sk()) {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 4;
cpsw_slaves[1].phy_addr = 5;
} else if (board_is_idk()) {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 0;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 0;
}
rv = cpsw_register(&cpsw_data);
if (rv < 0) {
printf("Error %d registering CPSW switch\n", rv);
return rv;
}
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
#endif
return rv;
}
#endif
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
return 0;
else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
return 0;
else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
return 0;
else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
return 0;
else
return -1;
}
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
void board_tee_image_process(ulong tee_image, size_t tee_size)
{
secure_tee_install((u32)tee_image);
}
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
