• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 402 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

Enabling SPI on beaglebone black

Linux/AM3358: Delay between SPI CS and clock

Hamid Kavian Athar
Intellectual 550 points

Part Number: AM3358

Tool/software: Linux

Hi there

I want to send some data to a micro controller with a beaglebone black (beagle bone is master). As shown in the picture, the delay between falling edge of cs and first rising edge of clock is too much. could you please tell me how to decrease it? the image is taken from a logic analyzer which its sampling rate is lower than SPI bitrate.

thanks a lot.