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Linux/TDA2SX: MMC boot issue

Murugan S22
Expert 1240 points

Part Number: TDA2SX

Tool/software: Linux

Hello all,

                 We are working on a custom board based on tda2sx.We are trying to boot from SD card and it stopping at " Waiting for root device PARTUUID=6c40cfeb-02..." . Im attaching the full log too.What could be the issue?

Fullscreen tda2sx_boot_log_1.txt Download 
U-Boot 2016.05 (Jun 18 2019 - 17:49:59 +0530)

CPU  : DRA752-GP ES2.0
Model: TI DRA742
Board: DRA74x EVM REV <NULL>
DRAM:  1 GiB
NAND:  0 MiB
MMC:   Timed out in wait_for_bb: status=1000
Timed out in wait_for_bb: status=1000
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
OMAP SD/MMC: 0, OMAP SD/MMC: 1
Timed out in wait_for_bb: status=1000
tps65903x: could not set LDO1 voltage.
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
Timed out in wait_for_bb: status=1000
tps65903x: could not set LDO1 voltage.
*** Warning - bad CRC, using default environment

Warning: fastboot.board_rev: unknown board revision
Timed out in wait_for_bb: status=1000
tps65903x: could not set LDO1 voltage.
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid GPT ***
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid Backup GPT ***
ERROR: cannot find partition: 'userdata'

at arch/arm/cpu/armv7/omap-common/utils.c:195/mmc_get_part_size()
Warning: fastboot.userdata_size: unable to calc
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst 
scanning bus for devices...
Found 0 device(s).
Net:   Could not get PHY for ethernet@48484000: addr 2

Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot:  0 
=> 
=> 
=> 
=> boot
Saving Environment to MMC...
Writing to redundant MMC(0)... done
Timed out in wait_for_bb: status=1000
tps65903x: could not set LDO1 voltage.
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
switch to partitions #0, OK
mmc0 is current device
Timed out in wait_for_bb: status=1000
tps65903x: could not set LDO1 voltage.
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
Timed out in wait_for_bb: status=1000
pcf8575_i2c_write_le16 i2c write failed to addr 21
SD/MMC found on device 0
3310280 bytes read in 1140 ms (2.8 MiB/s)
113295 bytes read in 63 ms (1.7 MiB/s)
Booting from mmc0 ...
Kernel image @ 0x82000000 [ 0x000000 - 0x3282c8 ]
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffe1000, end 8ffffa8e ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.4.84 (zinal@FSETBLR1LX043) (gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) ) #1 SMP PREEMPT Wed Jun 19 12:22:22 IST 2019
CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine model: TI DRA742
Reserved memory: created DMA memory pool at 0x0000000040300000, size 3 MiB
Reserved memory: initialized node cmem@40300000, compatible id shared-dma-pool
Reserved memory: regions without no-map are not yet supported
Reserved memory: created CMA memory pool at 0x0000000094000000, size 80 MiB
Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
Reserved memory: created CMA memory pool at 0x000000009f000000, size 16 MiB
Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
Reserved memory: regions without no-map are not yet supported
Reserved memory: regions without no-map are not yet supported
Reserved memory: created DMA memory pool at 0x00000000a8000000, size 64 MiB
Reserved memory: initialized node cmem@A8000000, compatible id shared-dma-pool
cma: Reserved 24 MiB at 0x00000000be400000
Forcing write-allocate cache policy for SMP
Memory policy: Data cache writealloc
OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier
DRA752 ES2.0
PERCPU: Embedded 12 pages/cpu @ef71a000 s18688 r8192 d22272 u49152
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 243456
Kernel command line: console=ttyO0,115200n8 root=PARTUUID=6c40cfeb-02 rw lpj=61475 rootfstype=ext4 rootwait
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 382468K/979968K available (4675K kernel code, 259K rwdata, 976K rodata, 288K init, 258K bss, 376316K reserved, 221184K cma-reserved, )
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc058d014   (5653 kB)
      .init : 0xc058e000 - 0xc05d6000   ( 288 kB)
      .data : 0xc05d6000 - 0xc0616d60   ( 260 kB)
       .bss : 0xc0618000 - 0xc0658b90   ( 259 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
NR_IRQS:16 nr_irqs:16 16
ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div
OMAP clockevent source: timer1 at 32786 Hz
Architected cp15 timer(s) running at 6.14MHz (phys).
clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
Switching to timer-based delay loop, resolution 162ns
clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
OMAP clocksource: 32k_counter at 32768 Hz
Console: colour dummy device 80x30
WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
This ensures that you still see kernel messages. Please
update your kernel commandline.
Calibrating delay loop (skipped) preset value.. 12.29 BogoMIPS (lpj=61475)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
/cpus/cpu@1 missing clock-frequency property
CPU0: update cpu_capacity 1024
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x800082c0 - 0x80008320
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (24.59 BogoMIPS).
CPU: All CPU(s) started in HYP mode.
CPU: Virtualization extensions available.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
omap_hwmod: l3_main_2 using broken dt data from ocp
omap_hwmod: vpe: no dt node
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2523 0xc0598e34()
omap_hwmod: vpe: doesn't have mpu register target base
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.84 #1
Hardware name: Generic DRA74X (Flattened Device Tree)
Backtrace: 
Function entered at [<c00124a8>] from [<c0012694>]
 r7:000009db r6:60000013 r5:00000000 r4:c05fcdbc
Function entered at [<c001267c>] from [<c01d67c8>]
Function entered at [<c01d6744>] from [<c002fa6c>]
 r7:000009db r6:c04fcc24 r5:00000009 r4:ef07de60
Function entered at [<c002f9e0>] from [<c002fad0>]
 r8:c0618000 r7:00000000 r6:00000000 r5:00000000 r4:c05e6348
Function entered at [<c002fa9c>] from [<c0598e34>]
 r3:c04ff18b r2:c04fced6
Function entered at [<c0598c70>] from [<c0021988>]
 r10:00000000 r9:c05cfb64 r8:c0618000 r7:00000000 r6:c0598c70 r5:c05dcd70
 r4:c05e6348
Function entered at [<c0021948>] from [<c0599898>]
 r7:c05c1820 r6:00000000 r5:c0618000 r4:c059986c
Function entered at [<c059986c>] from [<c0009728>]
Function entered at [<c0009690>] from [<c058ed84>]
 r9:c05cfb64 r8:c0618000 r7:c05c1820 r6:0000009d r5:c0618000 r4:00000002
Function entered at [<c058ec64>] from [<c0492b0c>]
 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0492af8 r4:c0618000
Function entered at [<c0492af8>] from [<c000f188>]
 r5:c0492af8 r4:00000000
---[ end trace 3bf577f2d545868e ]---
omap_hwmod: wd_timer2: no dt node
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2523 0xc0598e34()
omap_hwmod: wd_timer2: doesn't have mpu register target base
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.4.84 #1
Hardware name: Generic DRA74X (Flattened Device Tree)
Backtrace: 
Function entered at [<c00124a8>] from [<c0012694>]
 r7:000009db r6:60000013 r5:00000000 r4:c05fcdbc
Function entered at [<c001267c>] from [<c01d67c8>]
Function entered at [<c01d6744>] from [<c002fa6c>]
 r7:000009db r6:c04fcc24 r5:00000009 r4:ef07de60
Function entered at [<c002f9e0>] from [<c002fad0>]
 r8:c0618000 r7:00000000 r6:00000000 r5:00000000 r4:c05e1398
Function entered at [<c002fa9c>] from [<c0598e34>]
 r3:c04fc611 r2:c04fced6
Function entered at [<c0598c70>] from [<c0021988>]
 r10:00000000 r9:c05cfb64 r8:c0618000 r7:00000000 r6:c0598c70 r5:c05dcd70
 r4:c05e1398
Function entered at [<c0021948>] from [<c0599898>]
 r7:c05c1820 r6:00000000 r5:c0618000 r4:c059986c
Function entered at [<c059986c>] from [<c0009728>]
Function entered at [<c0009690>] from [<c058ed84>]
 r9:c05cfb64 r8:c0618000 r7:c05c1820 r6:0000009d r5:c0618000 r4:00000002
Function entered at [<c058ec64>] from [<c0492b0c>]
 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0492af8 r4:c0618000
Function entered at [<c0492af8>] from [<c000f188>]
 r5:c0492af8 r4:00000000
---[ end trace 3bf577f2d545868f ]---
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
OMAP GPIO hardware version 0.1
irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 !
omap-gpmc 50000000.gpmc: GPMC revision 6.0
gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
omap-gpmc 50000000.gpmc: nand: invalid 'nand-bus-width'
omap-gpmc 50000000.gpmc: failed to probe DT children
omap-gpmc: probe of 50000000.gpmc failed with error -22
hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 8 bytes.
omap4_sram_init:Unable to allocate sram needed to handle errata I688
omap4_sram_init:Unable to get sram pool needed to handle errata I688
OMAP DMA hardware revision 0.0
omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
edma 43300000.edma: memcpy is disabled
edma 43300000.edma: TI EDMA DMA engine driver
omap-iommu 40d01000.mmu: 40d01000.mmu registered
omap-iommu 40d02000.mmu: 40d02000.mmu registered
omap-iommu 58882000.mmu: 58882000.mmu registered
omap-iommu 55082000.mmu: 55082000.mmu registered
omap-iommu 41501000.mmu: 41501000.mmu registered
omap-iommu 41502000.mmu: 41502000.mmu registered
SCSI subsystem initialized
palmas 0-0058: IRQ missing: skipping irq request
omap_i2c 48070000.i2c: controller timed out
palmas: probe of 0-0058 failed with error -110
omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
Bluetooth: Core ver 2.21
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP socket layer initialized
Bluetooth: SCO socket layer initialized
clocksource: Switched to clocksource arch_sys_counter
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
bounce: pool size: 64 pages
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
omap_i2c 48072000.i2c: timeout waiting for bus ready
Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 301, base_baud = 3000000) is a 8250
console [ttyS0] enabled
4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 302, base_baud = 3000000) is a 8250
48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 303, base_baud = 3000000) is a 8250
48068000.serial: ttyS5 at MMIO 0x48068000 (irq = 304, base_baud = 3000000) is a 8250
48424000.serial: ttyS8 at MMIO 0x48424000 (irq = 305, base_baud = 3000000) is a 8250
[drm] Initialized drm 1.1.0 20060810
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] No driver support for vblank timestamp query.
[drm] Initialized vdrm 1.0.0 20110917 on minor 0
omapdss_dss 58000000.dss: master bind failed: -517
loop: module loaded
vmemexp device MAJOR num = 246
vmemexp class registered
/dev/vmemexp device registered
ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120
SCSI Media Changer driver v0.25 
ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst 
scsi host0: ahci
ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 345
davinci_mdio 48485000.mdio: davinci mdio revision 1.6
davinci_mdio 48485000.mdio: no live phy, scanning all
davinci_mdio: probe of 48485000.mdio failed with error -5
cpsw 48484000.ethernet: Detected MACID = 34:15:13:a3:6f:ce
cpsw 48484000.ethernet: cpsw: Detected MACID = 34:15:13:a3:6f:cf
PPP generic driver version 2.4.2
PPP Deflate Compression module registered
i2c /dev entries driver
ata1: SATA link down (SStatus 0 SControl 300)
omap_i2c 48060000.i2c: timeout waiting for bus ready
Invalid product ID code
omap_i2c 48060000.i2c: timeout waiting for bus ready
Invalid product ID code
mmc0: MAN_BKOPS_EN bit is not set
mmc0: new DDR MMC card at address 0001
mmcblk0: mmc0:0001 H8G4a2 7.28 GiB 
mmcblk0boot0: mmc0:0001 H8G4a2 partition 1 4.00 MiB
mmcblk0boot1: mmc0:0001 H8G4a2 partition 2 4.00 MiB
clock: dpll_abe_ck failed transition to 'locked'
clock: dpll_abe_ck failed transition to 'locked'
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:680 0xc03a15f8()
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.4.84 #1
Hardware name: Generic DRA74X (Flattened Device Tree)
Backtrace: 
Function entered at [<c00124a8>] from [<c0012694>]
 r7:000002a8 r6:20000093 r5:00000000 r4:c05fcdbc
Function entered at [<c001267c>] from [<c01d67c8>]
Function entered at [<c01d6744>] from [<c002fa6c>]
 r7:000002a8 r6:c054b6fc r5:00000009 r4:00000000
Function entered at [<c002f9e0>] from [<c002fb3c>]
 r8:ef781b88 r7:c05e3000 r6:c06185e0 r5:80000093 r4:ef02ca00
Function entered at [<c002fb18>] from [<c03a15f8>]
Function entered at [<c03a15cc>] from [<c03a17ac>]
 r5:80000093 r4:ef1f3500
Function entered at [<c03a1780>] from [<c0020c18>]
 r5:fffffff0 r4:c05e64b0
Function entered at [<c0020bf8>] from [<c00213f8>]
 r7:c05e3000 r6:c06185e0 r5:fffffff0 r4:c05e64b0
Function entered at [<c00211dc>] from [<c0021ad8>]
 r7:00000000 r6:a0000093 r5:c05e6510 r4:c05e64b0
Function entered at [<c0021aac>] from [<c0022a00>]
 r7:00000000 r6:00000001 r5:ef269a40 r4:00000000
Function entered at [<c00229a0>] from [<c0022a3c>]
 r7:00000000 r6:c0022a24 r5:ef26ae10 r4:ef26ae10
Function entered at [<c0022a24>] from [<c02c12b8>]
 r5:ef26ae10 r4:ef26ae74
Function entered at [<c02c127c>] from [<c02c134c>]
 r7:00000000 r6:ef26ae10 r5:ef218410 r4:ef26ae10
Function entered at [<c02c12e0>] from [<c02c208c>]
 r7:00000000 r6:c0022a24 r5:ef218410 r4:ef26ae10
Function entered at [<c02c1d38>] from [<c02c21a8>]
 r10:00000000 r9:c05d003c r8:ef781b88 r7:60000013 r6:00000004 r5:ef26ae74
 r4:ef26ae10
Function entered at [<c02c2154>] from [<c03a85f8>]
 r7:eeab7690 r6:c06105c0 r5:ef26ae10 r4:ef26ae10
Function entered at [<c03a8588>] from [<c02baae4>]
 r10:00000000 r9:c05d003c r8:c06105c0 r7:00000000 r6:c06105c0 r5:ef26ae10
 r4:c03a8588
Function entered at [<c02baa8c>] from [<c02b90c4>]
 r7:00000000 r6:c0651124 r5:00000000 r4:ef26ae10
Function entered at [<c02b8fac>] from [<c02b92b8>]
 r9:c05d003c r8:c0618000 r7:c06061d0 r6:c06105c0 r5:ef26ae44 r4:ef26ae10
Function entered at [<c02b9248>] from [<c02b77e8>]
 r7:c06061d0 r6:c02b9248 r5:c06105c0 r4:00000000
Function entered at [<c02b7774>] from [<c02b8c24>]
 r6:eeab0f80 r5:00000000 r4:c06105c0
Function entered at [<c02b8c04>] from [<c02b87e8>]
Function entered at [<c02b8714>] from [<c02b9b48>]
 r7:c05c1834 r6:00000000 r5:c0618000 r4:c06105c0
Function entered at [<c02b9aa4>] from [<c02ba9fc>]
 r5:c0618000 r4:c05b47e4
Function entered at [<c02ba9c4>] from [<c05b47fc>]
Function entered at [<c05b47e4>] from [<c0009728>]
Function entered at [<c0009690>] from [<c058ed84>]
 r9:c05d003c r8:c0618000 r7:c05c1834 r6:0000009d r5:c0618000 r4:00000007
Function entered at [<c058ec64>] from [<c0492b0c>]
 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0492af8 r4:c0618000
Function entered at [<c0492af8>] from [<c000f188>]
 r5:c0492af8 r4:00000000
---[ end trace 3bf577f2d5458690 ]---
omap_hwmod: atl: _wait_target_ready failed: -16
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147 0xc01f886c()
44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Idle): Data Access in Supervisor mode during Functional access
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.4.84 #1
Hardware name: Generic DRA74X (Flattened Device Tree)
Backtrace: 
Function entered at [<c00124a8>] from [<c0012694>]
 r7:00000093 r6:20000193 r5:00000000 r4:c05fcdbc
Function entered at [<c001267c>] from [<c01d67c8>]
Function entered at [<c01d6744>] from [<c002fa6c>]
 r7:00000093 r6:c051d7ff r5:00000009 r4:ef07dad0
Function entered at [<c002f9e0>] from [<c002fad0>]
 r8:80080003 r7:c051d744 r6:c051d69a r5:ef211450 r4:00000000
Function entered at [<c002fa9c>] from [<c01f886c>]
 r3:ef2112c0 r2:c051d7d1
Function entered at [<c01f863c>] from [<c00699f4>]
 r10:c0616928 r9:ef781b88 r8:00000000 r7:00000017 r6:ef05ac00 r5:00000000
 r4:ef2117c0
Function entered at [<c00699b4>] from [<c0069b24>]
 r10:00000000 r9:ef781b88 r8:ef008000 r7:00000017 r6:ef05ac60 r5:ef05ac60
 r4:ef05ac00
Function entered at [<c0069ae4>] from [<c006cf1c>]
 r7:00000017 r6:ef05ac60 r5:c05dd030 r4:ef05ac00
Function entered at [<c006ce6c>] from [<c0069168>]
 r7:00000017 r6:c05d23f8 r5:00000000 r4:00000000
Function entered at [<c0069148>] from [<c0069470>]
Function entered at [<c00693dc>] from [<c0009450>]
 r9:ef781b88 r8:ef07dd10 r7:fa213000 r6:ef07dc70 r5:c05d87fc r4:fa212000
Function entered at [<c0009400>] from [<c00130c0>]
Exception stack(0xef07dc70 to 0xef07dcb8)
dc60:                                     60000013 c054d130 ef07dd10 c0653bc0
dc80: c0653bc0 ef781b88 ef07dd70 c054d130 ef07dd10 ef781b88 00000000 ef07dccc
dca0: ef07dcd0 ef07dcc0 c0398254 c0496af0 60000013 ffffffff
 r7:ef07dca4 r6:ffffffff r5:60000013 r4:c0496af0
Function entered at [<c0496adc>] from [<c0398254>]
Function entered at [<c0398230>] from [<c03982bc>]
 r9:ef781b88 r8:00000000 r7:eeab7690 r6:ef07dd70 r5:00000000 r4:00000000
Function entered at [<c03982ac>] from [<c0399904>]
Function entered at [<c03998d4>] from [<c0399be4>]
 r10:00000000 r9:c05d003c r8:ef781b88 r7:eeab7690 r6:ef07dd70 r5:00000000
 r4:00000000
Function entered at [<c0399bb8>] from [<c03a8628>]
Function entered at [<c03a8588>] from [<c02baae4>]
 r10:00000000 r9:c05d003c r8:c06105c0 r7:00000000 r6:c06105c0 r5:ef26ae10
 r4:c03a8588
Function entered at [<c02baa8c>] from [<c02b90c4>]
 r7:00000000 r6:c0651124 r5:00000000 r4:ef26ae10
Function entered at [<c02b8fac>] from [<c02b92b8>]
 r9:c05d003c r8:c0618000 r7:c06061d0 r6:c06105c0 r5:ef26ae44 r4:ef26ae10
Function entered at [<c02b9248>] from [<c02b77e8>]
 r7:c06061d0 r6:c02b9248 r5:c06105c0 r4:00000000
Function entered at [<c02b7774>] from [<c02b8c24>]
 r6:eeab0f80 r5:00000000 r4:c06105c0
Function entered at [<c02b8c04>] from [<c02b87e8>]
Function entered at [<c02b8714>] from [<c02b9b48>]
 r7:c05c1834 r6:00000000 r5:c0618000 r4:c06105c0
Function entered at [<c02b9aa4>] from [<c02ba9fc>]
 r5:c0618000 r4:c05b47e4
Function entered at [<c02ba9c4>] from [<c05b47fc>]
Function entered at [<c05b47e4>] from [<c0009728>]
Function entered at [<c0009690>] from [<c058ed84>]
 r9:c05d003c r8:c0618000 r7:c05c1834 r6:0000009d r5:c0618000 r4:00000007
Function entered at [<c058ec64>] from [<c0492b0c>]
 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0492af8 r4:c0618000
Function entered at [<c0492af8>] from [<c000f188>]
 r5:c0492af8 r4:00000000
---[ end trace 3bf577f2d5458691 ]---
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147 0xc01f886c()
44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Idle): Data Access in Supervisor mode during Functional access
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.4.84 #1
Hardware name: Generic DRA74X (Flattened Device Tree)
Backtrace: 
Function entered at [<c00124a8>] from [<c0012694>]
 r7:00000093 r6:20000193 r5:00000000 r4:c05fcdbc
Function entered at [<c001267c>] from [<c01d67c8>]
Function entered at [<c01d6744>] from [<c002fa6c>]
 r7:00000093 r6:c051d7ff r5:00000009 r4:ef07db58
Function entered at [<c002f9e0>] from [<c002fad0>]
 r8:80080003 r7:c051d744 r6:c051d69a r5:ef211450 r4:00000000
Function entered at [<c002fa9c>] from [<c01f886c>]
 r3:ef2112c0 r2:c051d7d1
Function entered at [<c01f863c>] from [<c00699f4>]
 r10:c0616928 r9:eeab7740 r8:00000000 r7:00000017 r6:ef05ac00 r5:00000000
 r4:ef2117c0
Function entered at [<c00699b4>] from [<c0069b24>]
 r10:ef781e34 r9:eeab7740 r8:ef008000 r7:00000017 r6:ef05ac60 r5:ef05ac60
 r4:ef05ac00
Function entered at [<c0069ae4>] from [<c006cf1c>]
 r7:00000017 r6:ef05ac60 r5:c05dd030 r4:ef05ac00
Function entered at [<c006ce6c>] from [<c0069168>]
 r7:00000017 r6:c05d23f8 r5:00000000 r4:00000000
Function entered at [<c0069148>] from [<c0069470>]
Function entered at [<c00693dc>] from [<c0009450>]
 r9:eeab7740 r8:ef781b88 r7:fa213000 r6:ef07dcf8 r5:c05d87fc r4:fa212000
Function entered at [<c0009400>] from [<c00130c0>]
Exception stack(0xef07dcf8 to 0xef07dd40)
dce0:                                                       ef781b88 c054d130
dd00: 00000000 00000000 00000000 00000003 ef07dd70 eeab7690 ef781b88 eeab7740
dd20: ef781e34 ef07dd5c ef07dd48 ef07dd48 c0399be4 c03998d8 20000013 ffffffff
 r7:ef07dd2c r6:ffffffff r5:20000013 r4:c03998d8
Function entered at [<c0399bb8>] from [<c03a8628>]
Function entered at [<c03a8588>] from [<c02baae4>]
 r10:00000000 r9:c05d003c r8:c06105c0 r7:00000000 r6:c06105c0 r5:ef26ae10
 r4:c03a8588
Function entered at [<c02baa8c>] from [<c02b90c4>]
 r7:00000000 r6:c0651124 r5:00000000 r4:ef26ae10
Function entered at [<c02b8fac>] from [<c02b92b8>]
 r9:c05d003c r8:c0618000 r7:c06061d0 r6:c06105c0 r5:ef26ae44 r4:ef26ae10
Function entered at [<c02b9248>] from [<c02b77e8>]
 r7:c06061d0 r6:c02b9248 r5:c06105c0 r4:00000000
Function entered at [<c02b7774>] from [<c02b8c24>]
 r6:eeab0f80 r5:00000000 r4:c06105c0
Function entered at [<c02b8c04>] from [<c02b87e8>]
Function entered at [<c02b8714>] from [<c02b9b48>]
 r7:c05c1834 r6:00000000 r5:c0618000 r4:c06105c0
Function entered at [<c02b9aa4>] from [<c02ba9fc>]
 r5:c0618000 r4:c05b47e4
Function entered at [<c02ba9c4>] from [<c05b47fc>]
Function entered at [<c05b47e4>] from [<c0009728>]
Function entered at [<c0009690>] from [<c058ed84>]
 r9:c05d003c r8:c0618000 r7:c05c1834 r6:0000009d r5:c0618000 r4:00000007
Function entered at [<c058ec64>] from [<c0492b0c>]
 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0492af8 r4:c0618000
Function entered at [<c0492af8>] from [<c000f188>]
 r5:c0492af8 r4:00000000                                
---[ end trace 3bf577f2d5458692 ]---                    
NET: Registered protocol family 17                      
Bluetooth: RFCOMM TTY layer initialized                 
Bluetooth: RFCOMM socket layer initialized              
Bluetooth: RFCOMM ver 1.11
Bluetooth: BNEP (Ethernet Emulation) ver 1.3
Bluetooth: BNEP filters: protocol multicast
Bluetooth: BNEP socket layer initialized
Bluetooth: HIDP (Human Interface Emulation) ver 1.2
Bluetooth: HIDP socket layer initialized
omap_voltage_late_init: Voltage driver support not added
Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
ti_oppdm 4a003b20.oppdm: Unable to get vdd regulator:-517
Power Management for TI OMAP4+ devices.
Registering SWP/SWPB emulation handler
dmm 4e000000.dmm: initialized all PAT entries
omapdss_dss 58000000.dss: master bind failed: -517
Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
ti_oppdm 4a003b20.oppdm: Unable to get vdd regulator:-517
hctosys: unable to open rtc device (rtc0)
evm_1v8: disabling
aic_dvdd: disabling
vmmcwl_fixed: disabling
pbias_mmc_omap5: disabling
Waiting for root device PARTUUID=6c40cfeb-02...

Regards,

Murugan S

  • 0
    TI__Mastermind 42515 points

    Hi Murugan,

    can you enable additional mmc debug info as described in this document and see if it give some directions where the problem might be:

    Also can you make sure you have modified the device tree according to your board layout. In particular the voltage supply, you may refer to this part of dra7-evm.dts for an example:

    &mmc1 {                                                                                                                             
            status = "okay";                                                                                                            
            vmmc-supply = <&evm_3v3_sd>;                                                                                               
            vmmc_aux-supply = <&ldo1_reg>;
           ...
    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    Expert 1240 points

    Hi Yordan,

                                I enabled the mmc debug in menuconfig but could see any additional prints.Regarding the power supply,we are using tps659039.Im not sure if my configuration is correct.I'm attaching my dts file.Please have a look.

    Fullscreen 0815.dra7-evm.txt Download 
    /*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra74x.dtsi"
#include "dra7-evm-common.dtsi"

/ {
	model = "TI DRA742";
	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";

	memory {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1536 MB to 1024MB ITS */
	};

	reserved_mem: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp2_cma_pool: dsp2_cma@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9f000000 0x0 0x800000>;
			reusable;
			status = "okay";
		};
	};

	aliases {
		i2c7 = &disp_ser;
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		vin-supply = <&smps9_reg>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	};

	/*evm_3v3_sw: fixedregulator-evm_3v3_sw {*/
	evm_3v3_sw: fixedregulator-evm_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sw";
		vin-supply = <&sysen1>; 
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio5 8 0>;	/* gpio5_8 */
		startup-delay-us = <70000>;
		enable-active-high;
	};

	vtt_fixed: fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
	/*	vin-supply = <&sysen2>;*/
		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	};

        extcon_usb: extcon_usb1 {
                compatible = "linux,extcon-usb-gpio";
                id-gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
        };

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

};

&tpd12s015 {
	compatible = "ti,dra7evm-tpd12s015";
	pinctrl-names = "i2c", "ddc";
	pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
	pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;

	gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
		<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
		<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

	ddc-i2c-bus = <&i2c2>;
	mcasp-gpio = <&mcasp8>;
};

&dra7_pmx_core {
	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
		pinctrl-single,pins = <
			/* this pin is used as a GPIO via mcasp */
			0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
		>;
	};

	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
		pinctrl-single,pins = <
			0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
			0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
		>;
	};

	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
		pinctrl-single,pins = <
			0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
			0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};

	/* mmc1_pins_default: pinmux_mmc1_default_pins { */ /*ITS */
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

        /* ITS start */
        mmc1_pins_hs: pinmux_mmc1_hs_pins {
                pinctrl-single,pins = <
                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
                >;
        };

	/* mmc1_pins_hs: pinmux_mmc1_hs_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_clk.clk */
	/*		0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_cmd.cmd */
	/*		0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_dat0.dat0 */
	/*		0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_dat1.dat1 */
	/*		0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_dat2.dat2 */
	/*		0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)*/	/* mmc1_dat3.dat3 */
        /*		>;
	}; */

        mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
                pinctrl-single,pins = <
                        0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
                        0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
                        0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
                        0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
                        0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
                        0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
                >;
        };

	/* mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
	/*	pinctrl-single,pins = <
	/* 		0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
	/* 		0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
	/* 		0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
	/* 		0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
	/* 		0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
	/* 		0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
	/* 	>;
	}; */

        mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
                pinctrl-single,pins = <
                        0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_clk.mmc1_clk */
                        0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_cmd.mmc1_cmd */
                        0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_dat0.mmc1_dat0 */
                        0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_dat1.mmc1_dat1 */
                        0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_dat2.mmc1_dat2 */
                        0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)       /* mmc1_dat3.mmc1_dat3 */
                >;
        };

	/*mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
	/*	pinctrl-single,pins = <
	/*		0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_clk.clk */
	/*		0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_cmd.cmd */
	/*		0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat0.dat0 */
	/*		0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat1.dat1 */
	/*		0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat2.dat2 */
	/*		0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat3.dat3 */
	/*	>;
	}; */

        mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
                pinctrl-single,pins = <
                        0x354   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_clk.mmc1_clk */
                        0x358   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_cmd.mmc1_cmd */
                        0x35C   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_dat0.mmc1_dat0 */
                        0x360   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_dat1.mmc1_dat1 */
                        0x364   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_dat2.mmc1_dat2 */
                        0x368   (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)     /* mmc1_dat3.mmc1_dat3 */
                >;
        };

	/*mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
	/*	pinctrl-single,pins = <
	/*		0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
	/*		0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
	/*		0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
	/*		0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
	/*		0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
	/*		0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
	/*	>;
	}; */
        /* ITS end */

	mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs200_1_8v: mmc2_pins_hs200_1_8v {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc4_pins_default: mmc4_pins_default {
		pinctrl-single,pins = <
			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_hs: mmc4_pins_hs {
		pinctrl-single,pins = <
			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr12: mmc4_pins_sdr12 {
		pinctrl-single,pins = <
			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};

	mmc4_pins_sdr25: mmc4_pins_sdr25 {
		pinctrl-single,pins = <
			0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};
};

&dra7_iodelay_core {

	/* ITS Start */
        mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
                pinctrl-single,pins = <
                        0x620 (A_DELAY(560) | G_DELAY(365))     /* CFG_MMC1_CLK_OUT */
                        0x62C (A_DELAY(0)   | G_DELAY(0))       /* CFG_MMC1_CMD_OUT */
                        0x638 (A_DELAY(29)  | G_DELAY(0))       /* CFG_MMC1_DAT0_OUT */
                        0x644 (A_DELAY(0)   | G_DELAY(0))       /* CFG_MMC1_DAT1_OUT */
                        0x650 (A_DELAY(47)  | G_DELAY(0))       /* CFG_MMC1_DAT2_OUT */
                        0x65C (A_DELAY(30)  | G_DELAY(0))       /* CFG_MMC1_DAT3_OUT */
                        0x628 (A_DELAY(125) | G_DELAY(0))       /* CFG_MMC1_CMD_OEN */
                        0x634 (A_DELAY(43)  | G_DELAY(0))       /* CFG_MMC1_DAT0_OEN */
                        0x640 (A_DELAY(433) | G_DELAY(0))       /* CFG_MMC1_DAT1_OEN */
                        0x64C (A_DELAY(287) | G_DELAY(0))       /* CFG_MMC1_DAT2_OEN */
                        0x658 (A_DELAY(351) | G_DELAY(0))       /* CFG_MMC1_DAT3_OEN */
                >;
        };

        mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf {
                pinctrl-single,pins = <
                        0x194 (A_DELAY(150) | G_DELAY(95))      /* CFG_GPMC_A19_OUT */
                        0x1AC (A_DELAY(250) | G_DELAY(0))       /* CFG_GPMC_A20_OUT */
                        0x1B8 (A_DELAY(125) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
                        0x1C4 (A_DELAY(100) | G_DELAY(0))       /* CFG_GPMC_A22_OUT */
                        0x1D0 (A_DELAY(870) | G_DELAY(415))     /* CFG_GPMC_A23_OUT */
                        0x1DC (A_DELAY(30)  | G_DELAY(0))       /* CFG_GPMC_A24_OUT */
                        0x1E8 (A_DELAY(200) | G_DELAY(0))       /* CFG_GPMC_A25_OUT */
                        0x1F4 (A_DELAY(200) | G_DELAY(0))       /* CFG_GPMC_A26_OUT */
                        0x200 (A_DELAY(0)   | G_DELAY(0))       /* CFG_GPMC_A27_OUT */
                        0x368 (A_DELAY(240) | G_DELAY(0))       /* CFG_GPMC_CS1_OUT */
                        0x190 (A_DELAY(695) | G_DELAY(0))       /* CFG_GPMC_A19_OEN */
                        0x1A8 (A_DELAY(924) | G_DELAY(0))       /* CFG_GPMC_A20_OEN */
                        0x1B4 (A_DELAY(719) | G_DELAY(0))       /* CFG_GPMC_A21_OEN */
                        0x1C0 (A_DELAY(824) | G_DELAY(0))       /* CFG_GPMC_A22_OEN */
                        0x1D8 (A_DELAY(877) | G_DELAY(0))       /* CFG_GPMC_A24_OEN */
                        0x1E4 (A_DELAY(446) | G_DELAY(0))       /* CFG_GPMC_A25_OEN */
                        0x1F0 (A_DELAY(847) | G_DELAY(0))       /* CFG_GPMC_A26_OEN */
                        0x1FC (A_DELAY(586) | G_DELAY(0))       /* CFG_GPMC_A27_OEN */
                        0x364 (A_DELAY(1039) | G_DELAY(0))      /* CFG_GPMC_CS1_OEN */
                >;
        };

	/* ITS end */

	mmc1_iodelay_ddr50_rev11_conf: mmc1_iodelay_ddr50_rev11_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(572) | G_DELAY(540))	/* CFG_MMC1_CLK_IN */
			0x624 (A_DELAY(0) | G_DELAY(600))	/* CFG_MMC1_CMD_IN */
			0x630 (A_DELAY(403) | G_DELAY(120))	/* CFG_MMC1_DAT0_IN */
			0x63c (A_DELAY(23) | G_DELAY(60))	/* CFG_MMC1_DAT1_IN */
			0x648 (A_DELAY(25) | G_DELAY(60))	/* CFG_MMC1_DAT2_IN */
			0x654 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_IN */
			0x620 (A_DELAY(1525) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x62c (A_DELAY(55) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CLK_IN */
			0x620 (A_DELAY(1271) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
			0x624 (A_DELAY(229) | G_DELAY(0))	/* CFG_MMC1_CMD_IN */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x62C (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OUT */
			0x630 (A_DELAY(850) | G_DELAY(0))	/* CFG_MMC1_DAT0_IN */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(20) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
			0x63C (A_DELAY(468) | G_DELAY(0))	/* CFG_MMC1_DAT1_IN */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
			0x648 (A_DELAY(466) | G_DELAY(0))	/* CFG_MMC1_DAT2_IN */
			0x64C (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
			0x654 (A_DELAY(399) | G_DELAY(0))	/* CFG_MMC1_DAT3_IN */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
			0x65C (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(1063) | G_DELAY(17))	/* CFG_MMC1_CLK_OUT */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x62c (A_DELAY(23) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(2) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(600) | G_DELAY(400))	/* CFG_MMC1_CLK_OUT */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x62c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(30) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc2_iodelay_hs200_1_8v_rev11_conf: mmc2_iodelay_hs200_1_8v_rev11_conf {
		pinctrl-single,pins = <
			0x190 (A_DELAY(621) | G_DELAY(600))	/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(300) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
			0x1a8 (A_DELAY(739) | G_DELAY(600))	/* CFG_GPMC_A20_OEN */
			0x1ac (A_DELAY(240) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1b4 (A_DELAY(812) | G_DELAY(600))	/* CFG_GPMC_A21_OEN */
			0x1b8 (A_DELAY(240) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
			0x1c0 (A_DELAY(954) | G_DELAY(600))	/* CFG_GPMC_A22_OEN */
			0x1c4 (A_DELAY(60)  | G_DELAY(0))	/* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(1340)| G_DELAY(420))	/* CFG_GPMC_A23_OUT */
			0x1d8 (A_DELAY(935) | G_DELAY(600))	/* CFG_GPMC_A24_OEN */
			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
			0x1e4 (A_DELAY(525) | G_DELAY(600))	/* CFG_GPMC_A25_OEN */
			0x1e8 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
			0x1f0 (A_DELAY(767) | G_DELAY(600))	/* CFG_GPMC_A26_OEN */
			0x1f4 (A_DELAY(225) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
			0x1fc (A_DELAY(565) | G_DELAY(600))	/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(60) | G_DELAY(0))	/* CFG_GPMC_A27_OUT */
			0x364 (A_DELAY(969) | G_DELAY(600))	/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(180) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
	      >;
	};

	mmc2_iodelay_hs200_1_8v_rev20_conf: mmc2_iodelay_hs200_1_8v_rev20_conf {
		pinctrl-single,pins = <
			0x190 (A_DELAY(274) | G_DELAY(0))       /* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(162) | G_DELAY(0))       /* CFG_GPMC_A19_OUT */
			0x1a8 (A_DELAY(401) | G_DELAY(0))       /* CFG_GPMC_A20_OEN */
			0x1ac (A_DELAY(73) | G_DELAY(0))        /* CFG_GPMC_A20_OUT */
			0x1b4 (A_DELAY(465) | G_DELAY(0))       /* CFG_GPMC_A21_OEN */
			0x1b8 (A_DELAY(115) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
			0x1c0 (A_DELAY(633) | G_DELAY(0))       /* CFG_GPMC_A22_OEN */
			0x1c4 (A_DELAY(47) | G_DELAY(0))        /* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(935) | G_DELAY(280))     /* CFG_GPMC_A23_OUT */
			0x1d8 (A_DELAY(621) | G_DELAY(0))       /* CFG_GPMC_A24_OEN */
			0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
			0x1e4 (A_DELAY(183) | G_DELAY(0))       /* CFG_GPMC_A25_OEN */
			0x1e8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OUT */
			0x1f0 (A_DELAY(467) | G_DELAY(0))       /* CFG_GPMC_A26_OEN */
			0x1f4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OUT */
			0x1fc (A_DELAY(262) | G_DELAY(0))       /* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(46) | G_DELAY(0))        /* CFG_GPMC_A27_OUT */
			0x364 (A_DELAY(684) | G_DELAY(0))       /* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(76) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
	      >;
	};

	mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
		pinctrl-single,pins = <
			0x18c (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_IN */
			0x1a4 (A_DELAY(274) | G_DELAY(240))	/* CFG_GPMC_A20_IN */
			0x1b0 (A_DELAY(0) | G_DELAY(60))	/* CFG_GPMC_A21_IN */
			0x1bc (A_DELAY(0) | G_DELAY(60))	/* CFG_GPMC_A22_IN */
			0x1c8 (A_DELAY(514) | G_DELAY(360))	/* CFG_GPMC_A23_IN */
			0x1d4 (A_DELAY(187) | G_DELAY(120))	/* CFG_GPMC_A24_IN */
			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
			0x1ec (A_DELAY(0) | G_DELAY(60))	/* CFG_GPMC_A26_IN */
			0x1f8 (A_DELAY(121) | G_DELAY(60))	/* CFG_GPMC_A27_IN */
			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(174) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
			0x1ac (A_DELAY(168) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
			0x1b8 (A_DELAY(136) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
			0x1c4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(879) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
			0x1e8 (A_DELAY(34) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
			0x1f4 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(11) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
		>;
	};

	mmc2_iodelay_ddr_1_8v_rev20_conf: mmc2_iodelay_ddr_1_8v_rev20_conf {
		pinctrl-single,pins = <
			0x18c (A_DELAY(270) | G_DELAY(0))	/* CFG_GPMC_A19_IN */
			0x1a4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_IN */
			0x1b0 (A_DELAY(170) | G_DELAY(0))	/* CFG_GPMC_A21_IN */
			0x1bc (A_DELAY(758) | G_DELAY(0))	/* CFG_GPMC_A22_IN */
			0x1c8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A23_IN */
			0x1d4 (A_DELAY(81) | G_DELAY(0))	/* CFG_GPMC_A24_IN */
			0x1e0 (A_DELAY(286) | G_DELAY(0))	/* CFG_GPMC_A25_IN */
			0x1ec (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_IN */
			0x1f8 (A_DELAY(123) | G_DELAY(0))	/* CFG_GPMC_A27_IN */
			0x360 (A_DELAY(346) | G_DELAY(0))	/* CFG_GPMC_CS1_IN */
			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(55) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
			0x1ac (A_DELAY(422) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1b4 (A_DELAY(642) | G_DELAY(0))	/* CFG_GPMC_A21_OEN */
			0x1b8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OUT */
			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
			0x1c4 (A_DELAY(128) | G_DELAY(0))	/* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A23_OUT */
			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
			0x1dc (A_DELAY(395) | G_DELAY(0))	/* CFG_GPMC_A24_OUT */
			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
			0x1e8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OUT */
			0x1f0 (A_DELAY(623) | G_DELAY(0))	/* CFG_GPMC_A26_OEN */
			0x1f4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OUT */
			0x1fc (A_DELAY(54) | G_DELAY(0))	/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OUT */
		>;
	};

	mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
		pinctrl-single,pins = <
			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
			0x848 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_OUT */
			0x84c (A_DELAY(96) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
			0x870 (A_DELAY(582) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
			0x87c (A_DELAY(391) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
			0x888 (A_DELAY(561) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
			0x894 (A_DELAY(588) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
		pinctrl-single,pins = <
			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
			0x848 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_OUT */
			0x84c (A_DELAY(307) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
			0x870 (A_DELAY(785) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
			0x87c (A_DELAY(613) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
			0x888 (A_DELAY(683) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
			0x894 (A_DELAY(835) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
		pinctrl-single,pins = <
			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
			0x848 (A_DELAY(2651) | G_DELAY(0))	/* CFG_UART1_CTSN_OUT */
			0x84c (A_DELAY(1572) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
			0x870 (A_DELAY(1913) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
			0x87c (A_DELAY(1721) | G_DELAY(0))	/* CFG_UART2_RTSN_IN */
			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
			0x888 (A_DELAY(1891) | G_DELAY(0))	/* CFG_UART2_RXD_IN */
			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
			0x894 (A_DELAY(1919) | G_DELAY(0))	/* CFG_UART2_TXD_IN */
			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
		>;
	};

	mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
		pinctrl-single,pins = <
			0x840 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_CTSN_IN */
			0x848 (A_DELAY(1147) | G_DELAY(0))	/* CFG_UART1_CTSN_OUT */
			0x84c (A_DELAY(1834) | G_DELAY(0))	/* CFG_UART1_RTSN_IN */
			0x850 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OEN */
			0x854 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART1_RTSN_OUT */
			0x870 (A_DELAY(2165) | G_DELAY(0))	/* CFG_UART2_CTSN_IN */
			0x874 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OEN */
			0x878 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_CTSN_OUT */
			0x87c (A_DELAY(1929) | G_DELAY(64))	/* CFG_UART2_RTSN_IN */
			0x880 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OEN */
			0x884 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RTSN_OUT */
			0x888 (A_DELAY(1935) | G_DELAY(128))	/* CFG_UART2_RXD_IN */
			0x88c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OEN */
			0x890 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_RXD_OUT */
			0x894 (A_DELAY(2172) | G_DELAY(44))	/* CFG_UART2_TXD_IN */
			0x898 (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OEN */
			0x89c (A_DELAY(0) | G_DELAY(0))		/* CFG_UART2_TXD_OUT */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

/* PMIC node for ITS FS:NIRAJ */

        tps659039: tps659039@58 {
                compatible = "ti,tps659038";
                reg = <0x58>;

                interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
                interrupt-controller;
                #interrupt-cells = <2>;

                ti,system-power-controller;

                tps659039_pmic {
                        compatible = "ti,tps659038-pmic";

                        tps659039_regulators: regulators {
                                smps123_reg: smps123 {
                                        /* VDD_MPU_1V15 */
                                        regulator-name = "smps123";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
				smps45_reg: smps45 {
                                        /* VDD_DSPEVE_1V06 */
                                        regulator-name = "smps45";
                                        regulator-min-microvolt = <1020000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
				smps6_reg: smps6 {
                                        /* VDD_GPU_1V06 */
                                        regulator-name = "smps6";
                                        regulator-min-microvolt = <1020000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
				smps8_reg: smps8 {
                                        /* VDD_IVA_1V06 */
                                        regulator-name = "smps8";
                                        regulator-min-microvolt = <1020000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
				smps7_reg: smps7 {
                                        /* VDD_CORE_1V15 */
                                        regulator-name = "smps7";
                                        regulator-min-microvolt = <1020000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
				smps9_reg: smps9 {
                                        /* VDDS_1V8 */
                                        regulator-name = "smps9";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };

                                ldo1_reg: ldo1 {
                                        /* MMC1_3V3  */
                                        regulator-name = "ldo1";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                        regulator-allow-bypass;
                                };

				 ldo2_reg: ldo2 {
                                        /* VDSHV5_3V3 */
                                        regulator-name = "ldo2";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-boot-on;
                                        regulator-always-on;
                                };

                                ldo3_reg: ldo3 {
                                        /* VDDA_1V8_PHY */
                                        regulator-name = "ldo3";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };

                                ldo9_reg: ldo9 {
                                        /* VDD_RTC_1V05 */
                                        regulator-name = "ldo9";
                                        regulator-min-microvolt = <10200000>;
                                        regulator-max-microvolt = <12000000>;
                                        regulator-boot-on;
                                };
				ldoln_reg: ldoln {
                                        /* VDDA_1V8_LDOLN */
                                        regulator-name = "ldoln";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-boot-on;
                                };
				ldousb_reg: ldousb {
                                        /* VUSB_3V3_SOC */
                                        regulator-name = "ldousb";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <3300000>;
                                        regulator-boot-on;
                                };
				/* REGEN1 is unused */

				regen2: regen2 {
					/* Needed for PMIC internal resources */
					regulator-name = "regen2";
					regulator-boot-on;
					regulator-always-on;
				};

				/* REGEN3 is unused */

				sysen1: sysen1 {
					/* PMIC_REGEN_3V3 */
					regulator-name = "sysen1";
					regulator-boot-on;
					regulator-always-on;
				};

				sysen2: sysen2 {
					/* PMIC_REGEN_DDR */
					regulator-name = "sysen2";
					regulator-boot-on;
					regulator-always-on;
				};
                        };
                };

                tps659039_power_button {
                        compatible = "ti,palmas-pwrbutton";
                        interrupt-parent = <&tps659039>;
                        interrupts = <1 IRQ_TYPE_NONE>;
                        wakeup-source;
                        ti,palmas-long-press-seconds = <6>;
                };
        };

	pcf_lcd: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		compatible = "ti,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
 

	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
	        adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		
		status = "okay";

		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};

	tlv320adc3101: tlv320aic3101@1b {
               #sound-dai-cells = <0>;
               compatible = "ti,tlv320adc3101";
               reg = <0x1b>;
               adc-settle-ms = <40>;
               adc3101-micbias-vg = <3>;               /* 3.3V */
	       gpio-reset = <&gpio5 11 GPIO_ACTIVE_LOW>;
               status = "okay";
	};
	
		/* RTC-MCP7940N */
	mcp7940x:mcp7940x@6f {
		compatible = "microchip,mcp7940x";
		reg = <0x6f>;
	};
};

i2c_p3_exp: &i2c2 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: gpio@26 {
		compatible = "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		vin6_brdmux: p1 {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};

	ov10633@37 {
		compatible = "ovti,ov10633";
		reg = <0x37>;

		mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
		port {
			onboardLI: endpoint {
				remote-endpoint = <&vin1a>;
				hsync-active = <1>;
				vsync-active = <1>;
				pclk-sample = <0>;
			};
		};
	};

	disp_ser: serializer@1b {
		compatible = "ti,ds90uh925q";
		reg = <0x1b>;

		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&evm_3v3_sw>;
	/*vmmc-supply = <&evm_3v3_sd>;*/
	vmmc_aux-supply = <&ldo1_reg>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is always hardwired.
	 */
	/* ITS cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; */
	ti,non-removable; /* ITS */
	max-frequency = <192000000>;
        pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
        pinctrl-0 = <&mmc1_pins_default>;
        pinctrl-1 = <&mmc1_pins_hs>;
        pinctrl-2 = <&mmc1_pins_sdr12>;
        pinctrl-3 = <&mmc1_pins_sdr25>;
        pinctrl-4 = <&mmc1_pins_sdr50>;
        pinctrl-5 = <&mmc1_pins_ddr50>;
        pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;

/* ITS
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev11_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
	pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev20_conf>;
	pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
*/
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&evm_3v3_sw>;
	bus-width = <8>;
	ti,non-removable; /* ITS */
	max-frequency = <192000000>;
	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
        pinctrl-2 = <&mmc2_pins_ddr_1_8v>;
        pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;

/* ITS 
	pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>;
	pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>;
	pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>;
	pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>;
*/
};

&mmc4 {
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;

	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1835";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&oppdm_mpu {
	vdd-supply = <&smps123_reg>;
};

&oppdm_dspeve {
	vdd-supply = <&smps45_reg>;
};

&oppdm_gpu {
	vdd-supply = <&smps6_reg>;
};

&oppdm_ivahd {
	vdd-supply = <&smps8_reg>;
};

&oppdm_core {
	vdd-supply = <&smps7_reg>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
};

&gpio7 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mac {
	status = "okay";
	dual_emac;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <2>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <3>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu0_dsp2 {
	status = "okay";
};

&mmu1_dsp2 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dcan1 {
	status = "ok";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&dsp2 {
	status = "okay";
	memory-region = <&dsp2_cma_pool>;
	mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
	timers = <&timer6>;
	watchdog-timers = <&timer13>;
};

&dss {
	status = "okay";

	vdda_video-supply = <&ldoln_reg>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		port@lcd3 {
			reg = <2>;

			dpi_out3: endpoint {
				data-lines = <24>;
			};
		};
	};
};

&hdmi {
	vdda-supply = <&ldo3_reg>;
};

&mcasp8 {
	/* not used for audio. only the AXR2 pin is used as GPIO */
	status = "okay";
};

video_in: &vin2a {
	status = "okay";
	endpoint@0 {
		slave-mode;
		remote-endpoint = <&onboardLI>;
	};
};

&bb2d {
	status = "okay";
};

    Regards,

    Murugan S

  • 0 in reply to Murugan S22
    TI__Mastermind 33590 points

    Hi,

    For MMC_DEBUG logs to show up, you have to increase the loglevel, try appending loglevel=9 to kernel bootargs and try.

    Does this board have both eMMC and SD card slot?
    Is the file system on SD card or eMMC?

    Regards,
    Vishal

  • 0 in reply to Vishal Mahaveer
    TI__Mastermind 33590 points

    Any update on the logs?