CCS/TDA3XEVM: Hard Fault Error

Hi David,

Are you configuring AMMU in your application?

Regards,

Rishabh

Hello Yordan,

Thank you for your reply.

I tried it with SYSBOOT configured as you suggested and with VISION_SDK_CONFIG set to 0 it still gives the same error

Cortex_M4_IPU1_C1: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.1.0.00012)

I tried it then with VISION_SDK_CONFIG set to 1 and it appeared to work! It didn't give the error and it appeared to finish my simple test program.

So I thought great, but then I tried it again and it failed again and hasn't work again since.

David

Hi Rishabh,

I'm using a test project created by code composer for the DRA78x using the template for the "Hello World" project, the code I changed to do a simple loop . I used a linker file from the VISION project, which puts the program code in the external DDR memory. I am not do any extra AMMU configuration beyond what is done with the default gel files. 

David

Cortex_M4_IPU1_C1: GEL Output:  ==================================================
Cortex_M4_IPU1_C1: GEL Output:  ========= TDA3xx PG3.0 device detected   =========
Cortex_M4_IPU1_C1: GEL Output:  ========= TDA3xx GP Device detected    ===========
Cortex_M4_IPU1_C1: GEL Output:  ========= TDA3xx 15x15 Device detected ===========
Cortex_M4_IPU1_C1: GEL Output:  ==================================================
Cortex_M4_IPU1_C1: GEL Output: --->>> All Control module lock registers are UNLOCKED <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> Starting  IPU A-MMU configurations... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> IPU A-MMU configuration completed. <<<---
Cortex_M4_IPU1_C1: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<---
Cortex_M4_IPU1_C1: GEL Output: ------------------------------------------------------------------------------------------
Cortex_M4_IPU1_C1: GEL Output: --->>> 15x15 Package Detected(SYSBOOT[7]=0)... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> CORE DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C1: GEL Output: --->>> CORE DPLL OPP  already locked, now unlocking.... 
Cortex_M4_IPU1_C1: GEL Output: --->>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: --->>> PER DPLL OPP 0 clock config in progress...
Cortex_M4_IPU1_C1: GEL Output: --->>> PER DPLL already locked, now unlocking 
Cortex_M4_IPU1_C1: GEL Output: --->>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: --->>> DSP_GMAC DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C1: GEL Output: --->>> DSP_GMAC DPLL already locked, now unlocking....
Cortex_M4_IPU1_C1: GEL Output: --->>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: --->>> EVE_VID_DSP DPLL OPP 0 clock config is in progress...
Cortex_M4_IPU1_C1: GEL Output: --->>> DSP DPLL already locked, now unlocking....
Cortex_M4_IPU1_C1: GEL Output: --->>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR3 initialization starts (TI 15x15 EVM)... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR DPLL clock config for 532MHz is in progress...
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR DPLL already locked, now unlocking....
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C1: GEL Output:        Launch full leveling
Cortex_M4_IPU1_C1: GEL Output:        Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C1: GEL Output:        as per HW leveling output
Cortex_M4_IPU1_C1: GEL Output:        HW leveling is now disabled. Using slave ratios from
Cortex_M4_IPU1_C1: GEL Output:        PHY_STATUSx registers
Cortex_M4_IPU1_C1: GEL Output: --->>> DDR3 532MHz Initialization is DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA3xx Begin All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C1: GEL Output:  --->>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C1: GEL Output:  --->>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<---
Cortex_M4_IPU1_C1: GEL Output:  --->>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C1: GEL Output:  --->>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA3xx End All Pad Configuration for Vision Platform <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA3xx Target Connect Sequence DONE !!!!!  <<<---
Cortex_M4_IPU1_C1: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C1: GEL Output: For STM based tracing on TI EVMs,
Cortex_M4_IPU1_C1: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C1: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C1: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.1.0.00012)

Hello Rishabh,

I'm trying on both cores, I just copied the GEL messages from the second one as they are the same.

David

Hello Rishabh,

As far as I can tell the DDR is stable. Through the memory browser I can write and read to the memory and all appears correct.

I have some colleagues in a different country who have just received a TDA3x evaluation board and are going to try it. Their board is marked up just as TDA3x 15x15 EVM, while mine is TDA3x/DRA78x/DM50x 15x15 EVM, which appears to have some differences in the power supply area.

I have tried with a new target configuration with just IPI1_C0 connected but it still gives the same error.

David

Hello Rishabh,

I watched it for a while nothing changed.

David