PCIe interrupt set in RC-mode

Hi,

MCSDK is obsolete and please use the Processor SDK RTOS for C6678. We already have the PCIE interrupt test for INTA and MSI, see the http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#pcie

Regards, Eric

Hi.

Thank you for your answer.

PCIe not use in the  Processor SDK use product.

PCIe use in the MCSDK use product.

The customer requests an interrupt code
Customer was used as a polling as shown as see the example provided.
 
So I'm trying to test the interrupt method, but I can't execute ISR.

The 6678 content is not visible on the site provided.

Is there PCIe example project in the Processor SDK??

I'll check to see if there's an example of 6678 if you're for work tomorrow.
I'll see PCIe example project in Processor SDK.

Thank you.

Hi,

It is PCIE_evmc6678_wSoCFile_C66BiosExampleProject or PCIE_evmc6678_wSoCLib_C66BiosExampleProject inside the Processor SDK RTOS for C667x.

Regards, Eric

Thank you for your information.

I saw the project through the information sent, but I can't see INTA settings and Interrupt Service Routine (ISR).

In the notes to the project, i saw following information:
 - EVM EP sends 10 MSI and 10 INTA's to EVM RC (on certificate device and core combination)

Please tell me the INTA settings and ISR location. ??

Please tell me reason not be execute ISR. ??
As see above test screen shot occured interrupt INTA. but not execute ISR. EOI is 0 in the RC-mode (INTA interrupt)

I'm confused PCIe register informaion. but datasheet first use...

< pcie.h > application register structure

< datasheet >

Hi,

I am sorry, there is no PCIE interrupt example for Keystone device. The existing ones (10 INTA, 10 MSI) are for the AM57 and AM65.

But we still tested the PCIE interrupt on C66x devices (it is between a Linux PC and a C667x), you can look at the \mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_interrupt\src\pcieboot_interrupt.c.

Although this is a boot example, but you can extract the setup code for you (the code is not big): those platform init, UART you can ignore. There is an ISR also.

Then, how do you generate an interrupt from Linux side: there is inside mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c

/* Note: From PCIE specification, legacy interrupts cannot be generated from RC and be passed downstream.
The example below is just making use of the facility that RC can access EP side register to generate
a generic interrupt on local (EP) side using one of the event inputs of Interrupt Controller (INTC).
There is no real interrupt signal sent over the PCIe link */
printk ("Generating interrupt to DSP ...\n");
iowrite32(1, ptrReg + LEGACY_A_IRQ_STATUS_RAW/4);

This is actually by setting the IRQ_STATUS_RAW register. Without the Linux machine, I believe you just write the local DSP  IRQ_STATUS_RAW, you should enter the ISR.

Regards, Eric

Hi.

Thank you for your reply.

As you can see from the screen I tested, interrupts also occurred. (In RC-Mode)
(LEGACY A Interrupt Enabled Status Register 0x000001)
And I saw interrupt mapping, but there's nothing wrong. (cfg)

There must be something I don't know.
I asked why ISR was not implemented, but I can't understand the answer.

I'll investigate further.

Hi,

In the pcie_sample.c, there is no ISR code for the C667x. We didn't develop that.

In the \mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_interrupt\src\pcieboot_interrupt.c, there is ISR code and interrupt is hooked by using CSL level code. The PCIE INTA is system interrupt 50, this is a second interrupt input to CIC0, the CIC0 output is CIC0_OUT3 on core 0. This is connected to VectID = 4. This is code was tested and should work.

I saw you configured the interrupt using SYSBIOS, system interrupt 50=====> CIC0_OUT32. You may try the CSL level code first and debug why your way didn't work. Also there is a WIKI http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices you can refer.

Regards, Eric

Hi.

Thank you for your answer.

I'll check your answers.

I was testing without an EP by setting up RC-mode with evmc6678.
It was a test to confirm whether the ISR was executed.

During the data survey, I could see the contents of a similar test.
e2e.ti.com/.../223849

ISR runs only were received through PCIe lines, it said.

Is correct??

I thought the ISR needed to be implemented without an EP.

I'll investigate further.

Hi,

"ISR runs only were received through PCIe lines, it said."

"I thought the ISR needed to be implemented without an EP."======> In the real world, the EP sends the interrupt to RC. The INTA/B/C/D and MSI are in-band signals in PCIE, this is to emulate the dedicated interrupt lines for INTA/B/C/D in the legacy PCI. You don't need EP to develop your ISR code, but how do you plan to test it working? Ideally you use two board, one is RC and the other is EP for this test.

If you only have one board, for debug purpose how ISR worked, you may use one C6678 as the RC (without the EP), and manually (or code) change the LEGACY_A_IRQ_STATUS_RAW register. 

Regards, Eric

Hi.

Thank you for your reply.

The above test screen used 1 in the LEGACY_A_IRQ_STATUS_RAW register to confirm that there was an interrupt (1) in the LEGACY_A_IRQ_STATUS register.
However, the ISR was not implemented.

I'm preparing the code in advance before I visit the customer.(Use one evmc6678 board)

When ISR code is confirmed, it is planning to visit customers and test customer board (RC) and FPGA (EP).
Since only ISR has not been executed, it is expected to be an interrupt mapping setup problem. The existing PCIE_interrupt example settings that you answered and my existing settings did not run ISR either.

I have a question.
In Status and Command Register (+1004h), Bit19 is INT_STAT. Indicates interrupt reception.

Interrupts occurred (1) on LEGACY_A_IRQ_STATUS, but INT_STAT is 0. It cannot be set to 1 because it has read properties only.

Isn't this bit related to the execution of Interrupt ISR?

I think I'm doing something wrong or unknown...

I'll investigate further.

Thank you very much.

It was not a problem with ISR(cfg) and ISR(CSL) settings.

ISR(cfg) set in PCIE sampleProject did not work.

When I tested on the new SYS/BIOS project, I was able to check the motion right away.

Have a good day. Until the day you come back. (--)(__);