AM3352: ACCESSTIME start timing

Hi Biser,

Thank you for quick reply.

If the timing of the datasheet is correct, is it correct that the signal changes after one cycle of GPMC_FCLK after the start of ACCESSTIME, when each ONTIME is set to 0 in the GPMC_CONFIG register?
In other words, is it correct with the understanding that the setting of ACCESSTIME must be +1 to the timing described in TRM?

Best Regards,
Shigehiro Tsuda

Hi Tsuda-san,

StartCycleTime (aka StartAccessTime) is the time when the address bus becomes valid. All signal control parameters are defined relative to StartCycleTime.

I have drawn a red line on the timing diagrams to show StartCycleTime.

In Figure 7-12, RDCYCLETIME and RDACCESSTIME are relative to StartCycleTime.

RDCYCLETIME (in ns) =  (RdCycleTime value) × (TimeParaGranularity + 1) × (GPMC_FCLK period).

With these timing diagrams that depict  asynchronous transfers, I believe they show a few internal GPMC_FCLK cycles to demonstrate that the internal GPMC_FCLK does not ever stop. But the external GPMC_CLK does not toggle for asynchronous transfers.


If each ONTIME (ie CSONTIME, ADVONTIME, OEONTIME) is set to 0 in the GPMC_CONFIG register... then those control signals will become active low at the same time as StartCycleTime (at the same time as the address bus becoming valid).

Regards,
Mark