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Unable to bring-up Ethernet PHY .

KONKUMUTTI SAIRAM
Prodigy 40 points
Part Number: DP83867E

Tool/software: Linux

Hi TI,

I am using ZYNQ ZC7030  customized processor board,where i am using TI-DP83867E PHY to the MAC of ZYNQ board.

In EVM (ZC706) board we were having marvel PHY which is replaced by TI-DP83867E PHY.

So, while booting it is showing error as below

1.PHY is not detected

2.GEM PHYINIT FAILED

3.no Ethernet found

and i am having doubt with my PHY_ADDRESS and i am using same address as our hardware engineer mention.

DP83867configurationstraps: RX_D0---->MODE-2[01]

RX_D1--->MODE-1[00],WHICH INDICATED phy_address as 01 which we mentioned in dtb.So what is solution for this .

How do i resolve it.

my dtb node at UBOOT,

&gem0 {
    status = "okay";
    phy-mode = "rgmii-id";
    phy-handle = <&ethernet_phy>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_gem0_default>;

    ethernet_phy: ethernet-phy@1 {
        reg = <1>;
        device_type = "ethernet-phy";
              ti,rx-internal-delay = <0x8>;
            ti,tx-internal-delay = <0xa>;
            ti,fifo-depth = <0x01>;
    };

Any help is accepted.

Regards,

sai.

  • 0
    TI__Mastermind 26320 points

    Hi,

    You may want to check following:

    1. Phy is out of reset. You can check RX_CLK, it shall show 25 MHz or 125 Mhz clock depending on the link speed.

    2. Connect a CAT5e cable and see whether link is coming up or not .

    3.  You need to check the Straps for PHY Address configured on PHY. 

    Regards,

    Geet

  • 0 in reply to Geet Modi
    Prodigy 40 points

    The above mentioned tests are already done and which looks good for us.

    1. PHY reset is initially high and on POR it goes low for about 1ms and comes back to 1 which we measured on oscilloscope. But the question is in the datasheet, it is mentioned that minimum time the reset should be held low is for a minimum of 1us. Is there any problem if I reset it for 1ms?

     ->RX clk is 125MHZ which we saw it on oscilloscope.


    2. Connected the cat5e cable but the link is not ready after the booting.

    3. Checked the straps and accordingly mentioned  the phy address in DTB.

    Above mentioned are the DTB and strap modes we are using.

    4. At uboot we looked at mii info where we see all zeros.


    We are struck now.

    Please let us know if there are any checkpoint we have to do in order to debug and make it work.




  • 0 in reply to KONKUMUTTI SAIRAM
    TI__Mastermind 26320 points

    Hi,

    It's needs minimum of 1us. More is ok.

    If you are observing 125MHz clock, it means your link is up. Next you need to check the RGMII interface : why it is not transferring the data. You may want to do MII loopback and see whether you are receiving data back to FPGA.

    Regards.

    Geet

  • 0 in reply to Geet Modi
    TI__Mastermind 26320 points

    Hi,

    I am closing this thread. Incase you need further assistance, please open new thread and provide reference to this thread.

    Regards,

    Geet