Part Number: TMS320DM8168
The data sheet shows the following…
Min delay time and Max delay time are specified as percentages of clock cycle. Specification is given for tc min of 6.06ns (165MHz). However, customer operate at 148.5MHz which has a tc of 6.73ns. Normally expect min and max delay to be fixed. Thus as the clock rate slows down timing margins get easier to meet. By making the percentages this does not happen in the same way.
Is it correct to define them as percentages of 148.5MHz? This would mean …
Min Delay = 6.73ns * 0.27 = 1.82ns
Max Delay = 6.73ns * 0.8 = 5.39ns
allowing minimal incremental gain by slowing the clock
In Errata Advisory 2.1.47
Workaround: There are two options for a workaround:
1. The external device connected to the HDVPSS interface can capture data on the
rising edge.
2. External logic can be used to invert (or delay) the clock to provide adequate setup
and hold times to meet the requirements of the external device.
for #1 a max delay of Tc*0.8 is impossible to capture data on rising edge
Also this advisory states that HDPVSS Out only supports falling edge clock and points us to SPRS614F for more information. SPRS614F makes no mention of this, so there is a lack of clarity to the timing on this interface.
Need clarification since datasheet and errata have invalid information
