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TMS320C6654: What's the state of C6654(C6652) before and after DVDD15 wakes up?

M_N_
Intellectual 690 points
Part Number: TMS320C6654

Hi,

This issue is relative to ".

In short, more than half of DSPs on our custom boards couldn't access to DDR3.

Our team are still investigating the cause of DDR accessing problem.

In that, we noticed that there is sure way to succeed to access DSP to DDR3.

That is the power restoring of DVDD15.

After correct power sequence and correct reset sequence, NG board couldn't be loaded by.gel.

From then, DVDD15 having turning to low once and turning to active, NG board could be loaded by.gel.

we didn't vary other power supplying and POR & RESETFULL remained released.

As a next step, I burned the FW to nor flash on the NG board and tried to execute spi boot from nor flash.

This case, after correct power sequence and correct reset sequence, DSP didn't start to read the FW from nor flash,

however restoring the DVDD15, DSP started to read the FW and booting was successful.

From above, I want to know the state of the DSP when DSP couldn't start spi boot.

I recognize that DVDD15 is used for I/O voltage, but it seems that this power holds a very important role as boot.

I already confirmed boot manual from TI, but details were not described as the DSP's behavior when DVDD15 is supplied.

What does it happen when DVDD15 firstly wakes up, and what's the state of DSP then ? waiting? hunging?

regards,

  • 0
    TI__Guru**** 161600 points

    Hi,

    I recognize that DVDD15 is used for I/O voltage, but it seems that this power holds a very important role as boot.

    I already confirmed boot manual from TI, but details were not described as the DSP's behavior when DVDD15 is supplied.

    The DVDD15 is 1.5-V DDR3 IO supply it powers all DDR3 memory controller peripheral I/O buffers, its filtered versions are also PCIE Serdes & SGMII SerDes regulator supplies. So when DVDD15 wakes up it powers the DDR3 IO buffers.

    This power supply is important part of the power-up sequence, and you must make sure it is ramped up, as described in Section 6.3.1.1 Core-Before-IO Power Sequencing (pay attention to note 4a in Table 6-2. Core-Before-IO Power Sequencing) or as described in Section 6.3.1.2 IO-Before-Core Power Sequencing (Pay attention to 4a in Table 6-3 IO-Before-Core Power Sequencing).  

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 690 points

    Hi,

    >>Pay attention to 4a in Table 6-3 IO-Before-Core Power Sequencing

    Of course we confirmed that, and the sequence is in compliance.

    If each power ramping up with correct sequence, however DSP can't access to DDR3 or can't boot with SPI.

    Only way to make it works fine is "DVDD15 powering on again".

    What we want to know is not only that why DVDD15 need and when DVDD15 should be power on.

    We want to know what the DSP is something state before and after DVDD15 ramps up.

    Is the DSP waiting for DVDD15 to drive any controller? If there is something problem on DVDD15, Is the DSP into the any loop sequence?

    Please give me more detailed information about treatment of DVDD15.

    regards,

  • 0 in reply to Yordan Kovachev
    Intellectual 690 points

    This has not resolved at all.

    Please return the status to "Suggested answer".

  • 0 in reply to M_N_
    TI__Guru**** 161600 points

    Hi,


    There is nothing "special" bout DVDD15 described in the documents (device datasheet, Hardware Design Guide). 

    The only thing mentioned is in the DDR Design Requirements App note (section  8.2 DSP DDR3 Power Requirements) : "All DVDD15pins are designed to supply power to the DSP DDR3 IO buffers. As with the 1.5-V power pins, these must also be connected to a clean1.5-V supply rail."

    From then on you should pay attention to the power consumption, See Section 8.3 DDR3 Power Estimation, 8.4 DSP DDR3 Interface Power Estimation and Section 8.5 Sequencing – DDR3 and DSP


    Can you share the relevant DDR part of your schematics? Also can you check whether DDRRESET is released properly when the SoC is fully powered up?

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 690 points

    Hi Yordan,

    Thank you for your support.

    >>From then on you should pay attention to the power consumption, See Section 8.3 DDR3 Power Estimation, 8.4 DSP DDR3 Interface Power Estimation and >>Section 8.5 Sequencing – DDR3 and DSP

    It has no problem we think but we will confirm it just in case again.

    Our hardware team member will send you the part of schematics via TI support team of our country.

    I already explained the detailed issue to them so please continue to support us, thank you.

    regards,

  • 0 in reply to M_N_
    TI__Guru**** 161600 points

    Hi,

    Sure, I am also looping the hw designers to monitor this thread.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    M_N_,

    Regardless whether you see a behavior change by removing and then restoring DVDD15 after resets have been released, this is not valid and any conclusions drawn from it are questionable, at best.  Yordan has pointed you back to the power-clock-reset sequencing.  This MUST be followed.  I recommend that you carefully check each part of this.  Make sure that you check all supply inputs, all clock inputs and all reset inputs.  I speculate that you will find an issue related to one of these.  The device is fully qualified and in volume production at numerous customers.  There must be a design issue that is causing this behavior.

    Tom