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66AK2G12: Max VCO in Secondary PLL

Naoki Kawada
Guru 19890 points

Part Number: 66AK2G12

Hello,

My customer has a problem with USB Compliance Test on their custom board using K2G. It seems they failed in jitter requirement. 
They are generating USB clock via UART PLL (384Mhz output). This output has been divided by 16 (via BOOTCFG_USB0_CLKCTL ) to generate 24Mhz USB core clock.

From my understanding, maximizing VCO in PLL is needed in general in order to minimize the related clock jitter. Actually, TRM says :

Once the ROM boot is complete, reconfiguring the PLL with the intention of optimizing and
reducing output jitter may optionally be done, even if the PLL is already configured by the
ROM code. To minimize the overall output jitter, the PLL VCO output must be operated close
to, but not above, the maximum operating frequency of 4.2 GHz. Maximizing the VCO
frequency within the PLL is done by setting the PLL Output Divider as close as possible to
15 (OUTPUT_DIVIDE+1 must be an even number only). The PLLD value must be kept at 0
or as low as possible. The target PLLOUT frequency is therefore achieved by adjusting
PLLM.
PLL VCO Frequency = CLKIN / (PLLD+1) × (PLLM+1)
PLL OUT Frequency = VCO / (OUTPUT_DIVIDE+1)


So, I would like the customer to try maximizing VCO, but my question here is, the max VCO is really allowed up to 4.2Ghz. I feel that is pretty high. Could you comment ?

Best Regards,
NK

  • 0
    Guru 19890 points

    Hello,

    My customer tried the above PLL configurations and almost overcame the jitter problem, but still failed if they consider the worst case. In addition to Max VCO, could you please suggest ideas to improve the clock quality including HW modification? 

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points

    Hi Naoki,

    Does the customer have the proper filtering on the supply voltage for the PLL? A contributor to the jitter may be noise on the supply lines. Have the customer check to see if the noise levels are too high. Another contributor could be the jitter associated with the source clock for the system. Also check supply for the high frequency oscillator circuit.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19890 points

    Hello Bill,

    Thanks you for your answer. They have proper filter components for PLLs. But we found that no filter for DVDD33_USB pins. I seem this requirement has been added from datasheet RevD. Please take a look at the following section in the latest datasheet.

    7.3.1.6 USB PHY Power Supplies

    Do you think is this critical for USB Jitter ?

    Also, they are wondering if something extra handing might be need for LDO_USB_CAP pin. The datasheet says (footnote):

    This pin must always be connected through a 1-µF, ±50% decoupling capacitor with ESR of 10-100 mΩ to VSS with less than 0.5 nH of
    loop inductance.

    Is it okay if they just followed this ? Or, some additional handings needed for better clock ?

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    Guru 19890 points

    Hi,

    In addition, my customer has a question about F19 pin. This is DVDD18, but the EVM schematic implies this is regarded as USB_LDO. Please take a look at the following. This is a snapshot from EVM schematic.

    As per datasheet, this pin is just a DVDD18, but my customer is wondering if they might need some special handing for this pin to improve clock quality. 

    In summary, we would like to know your comment on:
    1. VCO max in Secondary PLL (Is 4.2Ghz max true?)
    2. critical issue or not in jitter perspective if DVDD33_USB without a specific filter 
    3. handing for LDO_USB_CAP pin (is it okay or not if we just follow datasheet footnote in jitter perspective) 
    4. and, special handing needed or not for DVDD18/USB_LDO (F19)


    Sorry for many questions.

    Best Regards,
    NK

  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points

    Hi Naoki,

    1. VCO max in Secondary PLL (Is 4.2Ghz max true?)

     - Yes that is true. All the PLLs use the same IP and have the same VCO max

    2. critical issue or not in jitter perspective if DVDD33_USB without a specific filter 

    - We have not included any special filtering on any of our platforms for DVDD33_USB

    3. handing for LDO_USB_CAP pin (is it okay or not if we just follow datasheet footnote in jitter perspective) 

    - Following the footnote should be sufficient. Meeting the loop inductance requirement usually requires placing the capacitor very close to the pin. I am assuming your design includes the capacitors. They are not shown in the schematic clip above. 

    4. and, special handing needed or not for DVDD18/USB_LDO (F19)

    - I checked with the design team concerning this. Since the 1.8V is used as a source voltage for the LDO, the expectation is that the output of the LDO will not be effected by the specified amount of noise on the 1.8V rail. That is why the pin name was grouped with the other DVDD1V8 power pins. 

    Have you checked to be sure that the routing of the USB signals meet the impedance requirements and meet the standards described in the High-Speed Interface Layout Guidelines?

    Regards,  Bill