This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/AM3359: GPMC configuration issue

Part Number: AM3359

Tool/software: Linux

Hi,

We are working on a custom board based on SITARA AM3359 Starterkit and is booting through eMMC.

SDK we are using is ti-processor-sdk-linux-am335x-evm-05.00.00.15 and kernel version is linux TI-SDK Kernel 4.14.40-g4796173fc5.

We've GPMC Interface between Processor & FPGA (Xilinx Artix 7). Processor is sending 8-bit (non multiplexed mode) data to FPGA via this interface. It is observed that

1. WE_n is going low first and then ALE signal is latched to the slave FPGA.

2. The pattern of ALE signal has a longer wait cycle after every 3rd ALE.

Please check the captured signal below

Although we could achieve 320 Mbps throughput but the data communication timing is not as per standard guidelines of TI SITARA processor.

Kindly help us identifying the reason behind the same and let us know the mode of communication.

Looking forward for the reply.

Regards

Vamsi

  • Hi,

    Please post your GPMC device tree settings, and also dump and post contents of GPMC_CONFIG[7:1]_x registers.

  • DTS Settings:

    &gpmc
    {
        pinctrl-names = "default";
        pinctrl-0 = <&gpmc_pins>;
        ranges = <2 0 0x01000000 0x01000000>; /* fpga */
        status = "okay";
        fpga{
            #address-cells = <1>;
            #size-cells = <1>;
            reg = <2 0 0x01000000>;
            bank-width = <2>;
     
            gpmc,sync-clk-ps=<0>; /* Minimum clock period for synchronous mode, in picoseconds */
     
            gpmc,cs-on-ns = <0>;        /* Assertion time */
            gpmc,cs-rd-off-ns = <10>;    /* Read deassertion time */
            gpmc,cs-wr-off-ns = <6>;    /* Write deassertion time */
     
            /* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
            gpmc,adv-on-ns = <1>;        /* Assertion time */
            gpmc,adv-rd-off-ns = <1>;    /* Read deassertion time */
            gpmc,adv-wr-off-ns = <1>;    /* Write deassertion time */
     
            /* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
            gpmc,we-on-ns = <1>;        /* Assertion time */
            gpmc,we-off-ns = <1>;        /* Deassertion time */
     
            /* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
            gpmc,oe-on-ns = <3>;        /* Assertion time */
            gpmc,oe-off-ns = <10>;        /* Deassertion time */
     
            /* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
            gpmc,access-ns = <9>;            /* Start-cycle to first data valid delay */
            gpmc,page-burst-access-ns = <1>;    /* Multiple access word delay */
            gpmc,rd-cycle-ns = <9>;            /* Total read cycle time */
            gpmc,wr-cycle-ns = <6>;            /* Total write cycle time */
     
     
            gpmc,burst-length= <8>;     //    Page/burst length. Must be 4, 8 or 16.
            gpmc,burst-wrap;        //    Enables wrap bursting
            gpmc,burst-read;         //    Enables read page/burst mode
            gpmc,burst-write;        //    Enables write page/burst mode
     
            gpmc,device-width=<1>; /* Total width of device(s) connected to a GPMC chip-select in bytes. The GPMC supports 8-bit and 16-bit devices and so this property must be 1 or 2. */
     
            //gpmc,sync-read;
            //gpmc,sync-write;
        };
    }


  • Hello Vamsi,

    I am wondering if you could please share the GPMC_CONFIG[7:1]_x registers.

    Regards,
    Krunal

  • Hello Vamsi,

    I will be closing the ticket but if you have any further questions, please feel free to open the ticket.

    Regards,
    Krunal