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RTOS/66AK2H14: MPAX (XMC & MSMC) issue with csl

Part Number: 66AK2H14
Other Parts Discussed in Thread: SYSBIOS, 66AK2H12

Tool/software: TI-RTOS

Hi everyone!

I had an exception issue using csl (see next posts), if I wrote directly in memory, I am able to change MPAX registers but with csl I had an error.

Does anyone have the same issue ? Anyone can help me ?

Regards,

François

  • #include <xdc/std.h>
    
    #include <xdc/runtime/Error.h>
    #include <xdc/runtime/System.h>
    #include <xdc/runtime/Log.h>
    
    #include <ti/sysbios/BIOS.h>
    
    #include <ti/sysbios/knl/Task.h>
    #include <ti/sysbios/knl/Clock.h>
    
    #include <ti/sysbios/hal/Core.h>
    #include <ti/sysbios/family/c64p/MemoryProtect.h>
    #include <ti/sysbios/family/c64p/Exception.h>
    #include <ti/sysbios/family/c66/Cache.h>
    
    #include <c6x.h>
    #include <csl_xmc.h>
    #include <csl_xmcAux.h>
    #include <csl_msmc.h>
    #include <csl_msmcAux.h>
    
    #include <string.h>
    
    
    /*
     *  ======== mem_protectFxn ========
     */
    Void mem_protectFxn(UArg a0, UArg a1)
    {
        Uint32 core_id = DNUM;
    
        /*
         * XMPAXH |31---------BADDR---------12|11---Reserved---5|4--SEGZ--0|
         * XMPAXL |31-----------RADDR-----------8|7---PERM---0|
         */
    
        /* DDR 1st segment */
        CSL_MSMC_SESMPAXH* ses_mpaxh = {0};
        CSL_MSMC_SESMPAXL* ses_mpaxl = {0};
    
        CSL_XMC_XMPAXH* mpaxh = {0};
        CSL_XMC_XMPAXL* mpaxl = {0};
    
        mpaxh->bAddr = 0xB0000000;
        mpaxh->segSize = 0x17;
    
        mpaxl->rAddr = 0xB0000000;
        mpaxl->sr = 1;
        mpaxl->sw = 1;
        mpaxl->ur = 1;
        mpaxl->uw = 1;
        mpaxl->ux = 1;
    
        CSL_XMC_setXMPAXH(6, mpaxh);
        CSL_XMC_setXMPAXL(6, mpaxl);
    
        ses_mpaxh->baddr = 0xB0000000;
        ses_mpaxh->segSz = 0x17;
    
        ses_mpaxl->raddr = 0xB0000000;
        ses_mpaxl->sr = 1;
        ses_mpaxl->sw = 1;
        ses_mpaxl->sx = 1;
        ses_mpaxl->ur = 1;
        ses_mpaxl->uw = 1;
        ses_mpaxl->ux = 1;
    #if 0
        CSL_MSMC_setSESMPAXH(0, 0, ses_mpaxh);
        CSL_MSMC_setSESMPAXL(0, 0, ses_mpaxl);
    #endif
    
        System_flush(); /* force SysMin output to console */
    }
    
    /*
     *  ======== main ========
     */
    Int main()
    {
        System_printf("enter main()\n");
        BIOS_start();    /* does not return */
        return(0);
    }
    

  • I got the following exception:

    [C66xx_0] enter main()
    A0=0x0 A1=0x0
    A2=0x1 A3=0x0
    A4=0x1 A5=0x81144c
    A6=0x7 A7=0x40000400
    A8=0x803994 A9=0x8006ac
    A10=0x0 A11=0x0
    A12=0x0 A13=0x0
    A14=0x0 A15=0x0
    A16=0x6c A17=0xa0
    A18=0x0 A19=0x0
    A20=0x90a6006 A21=0x6accda96
    A22=0x19b8dc2f A23=0xe29c3f94
    A24=0xba74c0b1 A25=0x262012c
    A26=0x27ff0000 A27=0x1000
    A28=0xf00 A29=0x400000
    A30=0x0 A31=0x0
    B0=0x80fc08 B1=0x0
    B2=0x8039b0 B3=0x807fe0
    B4=0xb0000000 B5=0xd7cc
    B6=0x816dd8 B7=0x15000101
    B8=0x816e34 B9=0x0
    B10=0x0 B11=0x0
    B12=0x0 B13=0x0
    B14=0x817750 B15=0x810458
    B16=0x64 B17=0x0
    B18=0x817318 B19=0xffffffff
    B20=0x4c B21=0x69
    B22=0x2a B23=0x2e
    B24=0x4e1c17a2 B25=0x20b149e8
    B26=0x20b149e4 B27=0x11e
    B28=0xd7cd6a85 B29=0x2
    B30=0x0 B31=0x814ad8
    NTSR=0x1000f
    ITSR=0xc
    IRP=0x80b5cc
    SSR=0x0
    AMR=0x0
    RILC=0x0
    ILC=0x0
    Exception at 0x803a00
    EFR=0x40000000 NRP=0x803a00
    UMC Exception MPFAR=0x0 MPFSR=0x110
    Security violation, Local L1/L2 cache memory Fault
    Supervisor Write violation, Fault ID=0x0
    ti.sysbios.family.c64p.Exception: line 256: E_exceptionMax: pc = 0x00803a00, sp = 0x00810458.
    xdc.runtime.Error.raise: terminating execution

  • Francois,

    I don`t have an example for 66AK2H12 but have an example that was tested on C6678 device where the CSL MPAX/XMC setup was confirmed to be working as part of a diagnostic self-test kit.

    Please review the function KeyStone_XMC_MPAX_setup in the Keystone Memory package and the test case for testing memory protection:

    K1_STK_Memory.zip

    Hope this example helps. The example was tested using bare-metal code. You can use the exception debugging by putting the 0x00803a00 to Program counter and check what code executes when the exception occurs. Also, can you try the same code without cache enabled on the region where memory protection is enabled.

    Regards,

    Rahul

  • Rahul,

    Thanks for your answer, I look into KeyStone_XMC_MPAX_setup function, but its not use CSL, so you do not have exception.

    The issue appear only using CSL,  I will not used CSL for the rest of my test, I think its the better way to do protection.

    Also thanks for the debugging tips. I'll get back to you in few days when I have something new.

    Best Regards,

    François

  • Ok. Let us know how the evaluation goes of the MPAX and XMC setting without the CSL or if you find any bug with the code we have shared here.

    Regards,

    Rahul