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AMIC110: AMIC110 Pin muxing

Thomas Hecht
Expert 1080 points

Part Number: AMIC110

Hello everybody,
I would like to use the AMIC110, the following peripherals are required:

1) EtherCat (ie 2x MII_PRUSS)
2) MDIO_PRUS
3) EMIF for the DDR RAM
4) parallel bus interface to the FPGA (GPMC).

I used the TI PinMux tool to map the peripherals. The following things have struck me: it is not possible to run the peripherals mentioned above in connection with a 16-bit-width GPMC, only an 8-bit data bus could be realized - do I see that correctly?

When configured as an 8-bit data bus GPMC the address A0 is also led out, why is the "Upper Byte Enable" signal still needed?

Another question: since the waite signals can not be muxed, can the waite cycles be configured in the AMIC110?

best regards

  • 0
    TI__Guru*** 125430 points

    Thomas Hecht said:
    I used the TI PinMux tool to map the peripherals. The following things have struck me: it is not possible to run the peripherals mentioned above in connection with a 16-bit-width GPMC, only an 8-bit data bus could be realized - do I see that correctly?

    Correct.

    Thomas Hecht said:
    When configured as an 8-bit data bus GPMC the address A0 is also led out, why is the "Upper Byte Enable" signal still needed?

    You don't need BE1n if that's what you're asking.

    Thomas Hecht said:
    Another question: since the waite signals can not be muxed, can the waite cycles be configured in the AMIC110?

    The WAIT0/WAIT1 pins are inputs that get used for cases where the external timing is not deterministic.  You're correct that these wouldn't be available to you.  Generally speaking those signals don't get used.  Most interfaces have a deterministic timing that you configure in the registers.

  • 0 in reply to Brad Griffis
    TI__Guru*** 125430 points

    PS.  Here's my *.pinmux file from the tool.  I assume yours looked the same or similar.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/AMIC110.pinmux

    One other item of note is the number of address pins.  If you were planning on a non-multiplexed configuration you would only have the following address pins available:

    • A0-A9
    • A20-A25

    Ideally the lower 10 bits gives you sufficient addressability to meet your needs.  If not you could still get a few more address bits, though the address map will look a bit disjointed from the AMIC110 perspective!

  • 0 in reply to Brad Griffis
    Expert 1080 points 
    Hello Bred, 
    Thanks for the answer. My pinmux file looks the same except for the BE1n (which had somewhat confused me).

    many thanks and a nice weekend

    best regards
    Thomas