Part Number: TMDSSK3358
Other Parts Discussed in Thread: AM3358, AMIC110, TLV320AIC3106
There is a very detailed diagram (Figure 22-17) of the Transmit Clock Generator in Section 22.3.5.1 of the AM335X and AMIC110 Sitara Processors Reference Manual (SPRUH73P). We have .wav files that have been recorded at an 8kHz sample rate, with 32 bits per frame (16 bit for the left channel and 16 bits for the right channel) (voice only). The TMDSSK3358 Evaluation board comes populated with the TI TLV320AIC3106 audio codec and it is connected to the AM3358 via the MCASP1 digital audio interface. The .wav files recorded with these settings play fine with this setup.
From Figure 22-17, it indicates that the transmit bit clock, ACLKX, can be either externally sourced from the ACLKX pin or internally generated within the AM3358 via either feeding an external AHCLKX to the CLKXDIV (divides by 1 to 32 in integer values) or by using the AUXCLK (which in the case of the TMDSSK3358 Evaluation Board is 24MHz (please correct me if I am wrong on this frequency as it is crucial for the rest of the explanation) and dividing the AUXCLK by the HCLKXCTL divider (divides by 1 to 4096 in integer values).
My question is: If the TMDSSK3358 Evaluation Board is using the internal AUXCLK of 24MHZ to generate the Transmit Bit clock (ACLKX and XCLK)., the bit clock for a sound file sampled at 8kHz with 2 channels of 16 bit date would have to be 8kHz * 16 * 2 = 256kHz. There is no integer division ratio to divide 24MHz by to get to a bit clock of 256kHz. the division ratio is 24MHz/256kHz = 93.75. How is the correct bit clock (ACLKX and XCLK) of 256kHz generated for the audio file that we are playing.
I'm asking this because understanding how this is accomplished is crucial as we are using the Octavo OSD3358-SM RED EVM, which contains the TI AM3358 Processor with the same TI TLV320AIC3106 audio codec interfaced via MCASP that is used on the TMDSSK3358 Evaluation Board with an external AHCLKX_IN of 24.576MHZ which would require that the CLKXDIV divider be able to divide by 96 to generate a 256kHz bit clock (its maximum division is 32) that the 8kHz sampled audio would require.
I appreciate any information on how the clocks are generated for this scenario.
Thank you.
Stephen Gilbert
Staff Engineer
NORTHROP GRUMMAN
Mission Systems
