Linux/AM3358: NAND-Flash and PRUETH

Hello Dave,

Making sure I understand your use case. Is this correct?:

You want to continue using PRU Dual Ethernet in your design. However, one of the PRU pins is also used by NAND for readybusy. You want to figure out if there is a way to still use NAND, while using that pin for a non-NAND function.

What version of software are you using?

Regards,

Nick

Hello Nick,

Your summary is correct.

I intend to use yocto 2.6 with corresponding meta-ti layer, as i already use them for other Designs.

Regards,

Dave

Hi Dave,

On the AM335, there are two signals WAIT0 and WAIT1 and I am wondering if both signals have pin conflicts. Also, is it possible to change any of the PRU pins to avoid pin conflicts?

Regards,
Krunal

Hi Krunal,

the documentation states that in order to boot from NAND you need to use WAIT0. As the PIN T17 is the only PIN that provides „GPMC_WAIT0“ and is also needed for „PR1_MII1_COL“, i wonder wether it is possible to use PRU Dual Ethernet combined with bootable NAND Flash as bootmedia.

Regards,

David

Hi David,

I did a quick search for BeagleBone Capes with NAND and dual ethernet PRU, but did not find any matches: elinux.org/Beagleboard:BeagleBone_Capes

I think the idea to switch from the WAIT pin during boot to the PRU pin after booting has legs. As you say, you can read a register in the NAND to determine ready/busy status. I don't know if the current GPMC driver performs this read, but you could find out and easily add it.

Sure enough, it appears the bootloader is restricted to using WAIT0, but you could wire it to both WAIT0 and WAIT1 if you wanted to use WAIT1 during application run-time instead of WAIT0.

Which pins of PRU1/0 are you using? Is the WAIT0 pin (T17) your only pin conflict?

Regards,
Mark

Hi Mark,

thanks for the answer.

with my current design, there is only the one conflict on T17.

As for the pins in usage, this is the relevant part of our device tree:

mdio_pruss1_pins_default: mdio_pruss1_pins_default {
	pinctrl-single,pins = <
		AM33XX_IOPAD(0x8c, PIN_OUTPUT | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_mdclk */
		AM33XX_IOPAD(0x88, PIN_INPUT | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_data */
	>;
};

mii0_pruss1_pins_default: mii0_pruss1_pins_default {
	pinctrl-single,pins = <
		AM33XX_IOPAD(0xa0, PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt0_clk */
		AM33XX_IOPAD(0xb4, PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_txd0 */
		AM33XX_IOPAD(0xb0, PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_txd1 */
		AM33XX_IOPAD(0xac, PIN_OUTPUT | MUX_MODE2) /* (R4) lcd_data3.pr1_mii0_txd2 */
		AM33XX_IOPAD(0xa8, PIN_OUTPUT | MUX_MODE2) /* (R3) lcd_data2.pr1_mii0_txd3 */
		AM33XX_IOPAD(0xcc, PIN_INPUT | MUX_MODE5) /* (U4) lcd_data11.pr1_mii0_rxd0 */
		AM33XX_IOPAD(0xc8, PIN_INPUT | MUX_MODE5) /* (U3) lcd_data10.pr1_mii0_rxd1 */
		AM33XX_IOPAD(0xc4, PIN_INPUT | MUX_MODE5) /* (U2) lcd_data9.pr1_mii0_rxd2 */
		AM33XX_IOPAD(0xc0, PIN_INPUT | MUX_MODE5) /* (U1) lcd_data8.pr1_mii0_rxd3 */
		AM33XX_IOPAD(0xa4, PIN_OUTPUT | MUX_MODE2) /* (R2) lcd_data1.pr1_mii0_txen */
		AM33XX_IOPAD(0xd8, PIN_INPUT | MUX_MODE5) /* (V4) lcd_data14.pr1_mii_mr0_clk */
		AM33XX_IOPAD(0xdc, PIN_INPUT | MUX_MODE5) /* (T5) lcd_data15.pr1_mii0_rxdv */
		AM33XX_IOPAD(0xd4, PIN_INPUT | MUX_MODE5) /* (V3) lcd_data13.pr1_mii0_rxer */
		AM33XX_IOPAD(0xd0, PIN_INPUT | MUX_MODE5) /* (V2) lcd_data12.pr1_mii0_rxlink */
		AM33XX_IOPAD(0xe8, PIN_INPUT | MUX_MODE2) /* (V5) lcd_pclk.pr1_mii0_crs */
		AM33XX_IOPAD(0x24, PIN_INPUT | MUX_MODE5) /* (T10) gpmc_ad9.pr1_mii0_col */
	>;
};

mii1_pruss1_pins_default: mii1_pruss1_pins_default {
	pinctrl-single,pins = <
		AM33XX_IOPAD(0x40, PIN_INPUT | MUX_MODE5) /* (R13) gpmc_a0.pr1_mii_mt1_clk */
		AM33XX_IOPAD(0x50, PIN_OUTPUT | MUX_MODE5) /* (R14) gpmc_a4.pr1_mii1_txd0 */
		AM33XX_IOPAD(0x4c, PIN_OUTPUT | MUX_MODE5) /* (T14) gpmc_a3.pr1_mii1_txd1 */
		AM33XX_IOPAD(0x48, PIN_OUTPUT | MUX_MODE5) /* (U14) gpmc_a2.pr1_mii1_txd2 */
		AM33XX_IOPAD(0x44, PIN_OUTPUT | MUX_MODE5) /* (V14) gpmc_a1.pr1_mii1_txd3 */
		AM33XX_IOPAD(0x60, PIN_INPUT | MUX_MODE5) /* (V16) gpmc_a8.pr1_mii1_rxd0 */
		AM33XX_IOPAD(0x5c, PIN_INPUT | MUX_MODE5) /* (T15) gpmc_a7.pr1_mii1_rxd1 */
		AM33XX_IOPAD(0x58, PIN_INPUT | MUX_MODE5) /* (U15) gpmc_a6.pr1_mii1_rxd2 */
		AM33XX_IOPAD(0x54, PIN_INPUT | MUX_MODE5) /* (V15) gpmc_a5.pr1_mii1_rxd3 */
		AM33XX_IOPAD(0x74, PIN_OUTPUT | MUX_MODE5) /* (U17) gpmc_wpn.pr1_mii1_txen */
		AM33XX_IOPAD(0x64, PIN_INPUT | MUX_MODE5) /* (U16) gpmc_a9.pr1_mii_mr1_clk */
		AM33XX_IOPAD(0x68, PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_rxdv */
		AM33XX_IOPAD(0x6c, PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_rxer */
		AM33XX_IOPAD(0x78, PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_rxlink */
		AM33XX_IOPAD(0xec, PIN_INPUT | MUX_MODE2) /* (R6) lcd_ac_bias_en.pr1_mii1_crs */
		AM33XX_IOPAD(0x70, PIN_INPUT | MUX_MODE5) /* (T17) gpmc_wait0.pr1_mii1_col */
	>;
};

As for the NAND driver, i haven't had time yet to look into the NAND driver structure, any pointers would be appreciated.

Regards,

Dave

Hi Mark,

Yes, i'm still working on this problem. I've decided to try and solve this problem by building a prototype.

I'll close this thread as resolved, but might open a new one on this topic.

Regards,
Dave