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UART 2

 

Dear All

We are trying to use UART 2

With the baud rate set to 115200, we see a bit period of about 4uS, i.e the speed is twice that expected.

The clocking of UART 2 differs from UARTs 0 and 1, both of these work OK.

Has anybody seen ths before?

Looking at clock.c, the three UARTS all derive their clocks from "fixedrate" is ths correct for UART2.

My clocks evaluate to the following:

Fixedrate: 24MHz

Commonrate: 108MHz

Armrate: 216MHz.

The processor we are using is a DM355  xxx A135

None of the three clock values give me a sensible baud rate setting.

Any suggestions please?

 

Thanks

Brendan

  • Brendan,

    This seems a little odd; UART2 is different from the other UART ports in that is support modem capabilities such as flow control, and the data-sheet also suggests it can support a mx baud rate of 5 MHz (compared to 1.5 MHz for the other UARTs); however, the way to control the baud rates appears to be the same across all UARTs.  Can you check DLL and DLH settings for all three UARTs to ensure they are all programmed for the same baud rate (see http://focus.ti.com/lit/ug/sprued9b/sprued9b.pdf for more details )

  • yes, a little odd indeed.

    By a process of trial and error, I have fond that the uart needs to be initialised with a clock value of 54MHz.

    Does this mean that it is actually being clocked at 54MHz internally?

    Probably not as all the other periferals running from SYSCLK2 seem to work OK.

    So in the tradition of good software engineering, I have applied a hack, setting the clocks to 54MHz, resolve to re-visit this when things are not quite so hectic.

    Any guesses as to how long it will be befor this comes back abd bites me?

     

     

  • Good catch.  You are correct, UART2 is driven by SYSCLK2 which runs at 108 MHz by default in our software.  UART0 and UART1 are clocked at 24 MHz by default. 

    When you say you changed the clock to 54 MHz, do you mean you changed SYSCLK2 to 54 MHz?  I would not advise this approach since many other peripherals are dependant on SYSCLK2 and although they may still function, they will function slower.  A better approach would be to keep SYSCLK2 at 108 MHz and use UART divisor registers (DLH and DLL) to achive the desired baud rate from UART2.

  • No I have not changes sysclk2

    Am I correct in assuming that by setting the UART clock to 54MHz that the driver determins the required settings for the divisor registers.

    That would explain why my quick fix works.

     

  • This is where I am a bit concerned; you see, SYSCLK2 is the input clock into UART2; the uart divisor registers are user to generate the internal UART2 clock which corresponds to the baud rate.  Therefore, unless your baud rate is 54 MHz, I am afraid that the the software may be modifying SYSCLK2 instead.  This would also make sense as far as the double clock rate you were initially seeing ( SYSCLK2 108 MHz default is twice the 54 MHz that produces your desired results).  That said, what baud rate are you seeing from UART2 now?

  • With the clock set to 54MHz, I am happily running at 115200, using termios to set the baud rate.

    Setting these clock values definitly has an effect on the UART.

    The other periferals I am using on that clock bus. MMC, USB and GPIO all work OK.

    The changes made to the clock values are in:

    board_dm355_evm.c:

    static struct plat_serial8250_port serial_platform_data[] = {
        {
            .membase = (char *) IO_ADDRESS(DAVINCI_UART0_BASE),
            .mapbase = (unsigned long) DAVINCI_UART0_BASE,
            .irq = IRQ_UARTINT0,
            .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
            .iotype = UPIO_MEM,
            .regshift = 2,
            .uartclk = 24000000,
        },
        {
            .membase = (char *) IO_ADDRESS(DAVINCI_UART1_BASE),
            .mapbase = (unsigned long) DAVINCI_UART1_BASE,
            .irq = IRQ_UARTINT1,
            .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
            .iotype = UPIO_MEM,
            .regshift = 2,
            .uartclk = 24000000,
        },
        {
            .membase = (char *) IO_ADDRESS(DM355_UART2_BASE),
            .mapbase = (unsigned long) DM355_UART2_BASE,
            .irq = IRQ_DM355_UARTINT2,
            .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
            .iotype = UPIO_MEM,
            .regshift = 2,
            .uartclk = 54000000,
        },
        {
            .flags = 0
        },
    };

    and in clock .c:

    static struct clk davinci_dm355_clks[] = {
        {
            .name = "ARMCLK",
            .rate = &armrate,
            .lpsc = -1,
            .flags = ALWAYS_ENABLED,
        },
        {
            .name = "UART0",
            .rate = &fixedrate,
            .lpsc = DAVINCI_LPSC_UART0,
            .usecount = 1,
        },
        {
            .name = "UART1",
            .rate = &fixedrate,
            .lpsc = DAVINCI_LPSC_UART1,
            .usecount = 1,
        },
        {
            .name = "UART2",
            //.rate = &fixedrate,
            //.rate = &commonrate,
            .rate = &div_by_two,   // - commonrate /2
            .lpsc = DAVINCI_LPSC_UART2,
            .usecount = 1,
        },