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TMS320C6678: PCIE root complex problem - there is link, can access to PCIE configuration space, but cannot access to the bar memory in the End point

Zvi Marks
Prodigy 70 points
Part Number: TMS320C6678

Hi,

I bring up pcie DSP root complex to the Xilinx FPGA ultrascale End point by chip to chip by the board.

I got link, the pcie training is passed and the dsp pcie root can access to "Pcie configuration space" on the FPGA End point.

When try to access by DSP Pcie root to internal memory of the End point its fail and noting is happens.

How I can to debug it?

the Xilinx FPGA ip is https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

I configured  bar0 to direct access and bar1 to dma port.

Thanks,

Zvi

  • 0
    Guru 13202 points

    Hello!

    If you can read config space, then link should be okay. For the matter of experiment you may try set up BARs and read them back to make sure programmed value was correct, and I anticipate that would be correct too.

    I suspect, that your difficulty is on FPGA side. Core you are using does not expose internal signals. Nevertheless, I would try to dig inside that core guts and find a signal like bar_hit of similar. That is one hot bus indicating which BAR current transaction matches to. Then triggering on either SOF of EOF on transaction interface check whether your BARs were reached. If that test passed, I would next plug onto memory mapped interface and monitor whether any AXI signal gets activated shortly after SOF/EOF.

    Hope this helps.

  • 0 in reply to Victor Kazmirenko
    Prodigy 70 points

    Hi,

    Thanks for the fast respond.

    The problem is solved :)

    When configure the bar0 base addr on the PCIE configuration space to 0x0 with size 1MB and for bars1 base addr to 0x100000 size 1MB, its worked. and by the way removed some of temporary configurations spare.

    Thanks,

    Zvi Marks