AM3352: NMI level timing

Holger,

The NMI pin connects directly to the interrupt controller.  Section 6.1.1.1 of the Technical Reference Manual specifies:

The INTC supports only level-sensitive incoming interrupt detection. A peripheral asserting an interrupt
maintains it until software has handled the interrupt and instructed the peripheral to deassert the interrupt.

In other words, the external device is expected to keep the interrupt asserted until it has been acknowledged.  Can the external device be configured to keep NMI asserted for a long period of time (e.g. till the software can react)?  If not, you might consider using a GPIO pin where you can configure an edge polarity.

Best regards,
Brad

Hello Brad,
I definitive need the minimum time for the nMI pin! The customer can adjust a longer time than 30ns.

Regards, Holger

Holger,

I want to clearly state that this pin does *not* function as NMI.  In other words, this pin is maskable same as any other interrupt.  For this reason the pin was named EXTINTn instead of its original name of nNMI.  I imagine the customer may have chosen this pin thinking that it is non-maskable, but that is not true.

In order to understand the timing of this pin, you need to look at the documentation of the Interrupt Controller (Chapter 6 "Interrupts" in the Technical Reference Manual).  Normally the connections to the interrupt controller happen inside the device (e.g. GPIO interrupt asserted by GPIO peripheral).  In your case, you actually have a pin that connects directly to the interrupt controller.  Ultimately your question relates to the timing of when that interrupt is recognized by the interrupt controller.  Please refer to Section 6.2.2 "INTC Processing Sequence".  In particular, note that in step 6 the ISR of a previously recognized interrupt runs.  During this time pending interrupts are not processed.  In step 7 the ISR sets NEWIRQAGR to re-enable interrupt processing in the interrupt controller.  In other words, the amount of time that it takes to recognize a pending interrupt is going to be variable.  Normally this variability doesn't matter since all the signaling happens internal to the SoC.  However, in the case of EXTINTn, you need to keep the interrupt asserted until it has been recognized.   So how much time will it take to recognize the interrupt?  That's going to depend on the size of your ISR's (i.e. software dependent).

FYI, the schematic checklist recommends using a GPIO pin instead of the EXTINTn pin to avoid this sort of scenario, i.e. it sounds like what you really want is an edge-triggered interrupt.  In that case, the edge will latch the interrupt into a GPIO register, and the GPIO peripheral will maintain the asserted interrupt to the interrupt controller until it has been acknowledged inside the ISR.  This will avoid the issue you're currently experiencing.

Best regards,
Brad

Hello Brad,
thanks for the answer. Customer has an additional question, what would be signal delay time from the EXTINTn pin to interrupt controller (or the fasted time to generate the interrupt).

Regards, Holger

Brad, please send me an answer. Regards, Holger.

I don't have that information.  I am trying to coordinate with others to see what we can provide.