Figure 98 of SPRU973 shows the sequence of TCP2 events is SA mode. I don't understand what initiates the TCP events.
Working left to right, the first event after "Soft reset" is XEVT. Why does the TCP generate this? Does it always do this after a reset? (It seems strange to me that a co-processor should take it on itself to request data.)
In response to this XEVT the CPU/DMA performs "Write input params" and the TCP follows with a second XEVT. How does the TCP know the params have been written? Do they need to be written in a specific order, with the last written value indicating the process is complete?
The CPU/DMA responds with a "Write input data" and the TCP issues a third XEVT. Again, how does the TCP know the data transfer is complete? I guess it could read the frame length and the start address and wait for the last value to be written, but I very much doubt it.
In response to the 3rd XEVT the CPU/DMA "Write the interleaver coefficients". And again, how does the TCP know this has finished before it kicks off the first MAP decode.
I suspect their is a single explanation for the points above - will someone please enlighten me! Many thanks.
(Having written the above I now realise that the EDMA3 would know when each of these transfers had completed - this isn't just a confusingly labelled figure is it?)