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66AK2H14: Does DDR3B could be setup at 32-bit ?

Francois P
Expert 1050 points

Part Number: 66AK2H14

Hi everyone!

I am trying to setup DDR3B in 32-bit, do you have any example of code in order to proceed.

Regards,

François

  • 0
    TI__Guru* 95265 points

    Hi,

    I looked at the GEL file under ccs_base\emulation\boards\xtcievmk2x\gel, we always setup DDR3B at 64-bit. Let me check if we have any example for 32-bit.

    Regards, Eric

  • 0 in reply to lding
    Expert 1050 points

    Hi Eric,

    Thanks,

  • 0 in reply to Francois P
    Expert 1050 points

    Hi Eric,

    I use a file without these defines:

    #define DDR3B_BASE_ADDR (0x21020000)
    #define DDR3B_STATUS   (*(int*)(DDR3B_BASE_ADDR + 0x00000004))
    #define DDR3B_SDCFG    (*(int*)(DDR3B_BASE_ADDR + 0x00000008))
    #define DDR3B_SDRFC    (*(int*)(DDR3B_BASE_ADDR + 0x00000010))
    #define DDR3B_SDTIM1   (*(int*)(DDR3B_BASE_ADDR + 0x00000018))
    #define DDR3B_SDTIM2   (*(int*)(DDR3B_BASE_ADDR + 0x0000001C))
    #define DDR3B_SDTIM3   (*(int*)(DDR3B_BASE_ADDR + 0x00000020))
    #define DDR3B_SDTIM4   (*(int*)(DDR3B_BASE_ADDR + 0x00000028))
    #define DDR3B_ZQCFG    (*(int*)(DDR3B_BASE_ADDR + 0x000000C8))
    #define DDR3B_TMPALRT  (*(int*)(DDR3B_BASE_ADDR + 0x000000CC))
    #define DDR3B_DDRPHYC  (*(int*)(DDR3B_BASE_ADDR + 0x000000E4))


    #define DDR3B_PHY_CFG_BASE (0x02328000)
    #define DDR3B_PIR    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000004))
    #define DDR3B_PGCR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000008))
    #define DDR3B_PGCR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000000C))
    #define DDR3B_PGCR2  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000008C))
    #define DDR3B_PGSR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000010))
    #define DDR3B_PGSR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000014))
    #define DDR3B_PTR0   (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000001C))
    #define DDR3B_PTR1   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000020))
    #define DDR3B_PTR2   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000024))
    #define DDR3B_PTR3   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000028))
    #define DDR3B_PTR4   (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000002C))
    #define DDR3B_DSGCR  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000040))
    #define DDR3B_DCR    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000044))
    #define DDR3B_MR0    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000054))
    #define DDR3B_MR1    (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000058))
    #define DDR3B_MR2    (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000005C))
    #define DDR3B_DTCR   (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000068))
    #define DDR3B_DTPR0  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000048))
    #define DDR3B_DTPR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x0000004C))
    #define DDR3B_DTPR2  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000050))
    #define DDR3B_PLLCR  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000018))

    #define DDR3B_ZQ0CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000184))
    #define DDR3B_ZQ1CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x00000194))
    #define DDR3B_ZQ2CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001A4))
    #define DDR3B_ZQ3CR1  (*(int*)(DDR3B_PHY_CFG_BASE + 0x000001B4))

    #define DDR3B_TEST_START_ADDRESS (0x60000000)

    #define DDR3B_TEST_END_ADDRESS   (DDR3B_TEST_START_ADDRESS + (4 * 100))

    #define DDR3B_BASE_ADDRESS            0x60000000

    That is explained the DDR3B couldn't be initialize.

    Thanks for your time I solved my issue.

    Regards,

    François