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Linux/PROCESSOR-SDK-AM437X: GPIO toggle delay

Part Number: PROCESSOR-SDK-AM437X

Tool/software: Linux

We have a modem connected to Sitara AM437x using SPI and GPIO lines. The modem uses the processor's GPIO input to indicate (on falling edge) that data is received. The processor then reads the modem's status and data registers through the SPI interface. The data rate is around a byte every 8 milliseconds.

Our application (written in C) polls on the GPIO input that informs us of data availability every 8 millisecond. However, the GPIO read (using both memmap and also the sys/class interface) sometimes takes more than that thereby resulting in overflow conditions (where we miss a read of a data byte).

For cases where we toggle an output GPIO pins in short interval (for example every 15 milliseconds) from an application, we have noticed challenges to keep up with the time (like in a realtime system).  We have tried both memmap and sys interface to access and toggle the GPIO pins.
Therefore, we have started to suspect an higher priority process/kernel module is preempting our application for long periods of time intermittently (sometimes we have noticed delays as long as 80 milliseconds) between togging the output GPIO (which we try to do every 15 milliseconds from the application).
We are using the Arago project's TI SDK 5.2.0.10 build for u-boot, kernel and root file system on which we are running our application.
  • Hi,

    TI does offer a RT preempt full kernel for the SDK version that you are using. The kernel you are using does have preemption enabled but will have some non-determinism association. You have two possible paths to look at. You could elevate your application to a priority >50 and use a scheduling policy that is called FIFO. I would recommend trying this step first to see if you can get the determinism you need. You could also switch to RT kernel based SDK as well as still do the higher priority and scheduling policy for the application. If you decide to change kernels I would recommend thinking about changing to the latest SDK as well. I admit this will be a time adder especially as this could involve modifying your DTS file to build under the newer kernel.  But a later kernel provides the option of picking bug fixes or feature additions.

    Here is a link that discusses the RT application development on the TI SDK that goes into more detail about what I mentioned above.

    RT Application development on Processor SDK Linux-rt

    Best Regards,

    Schuyler

  • Thank you Schuyler, I work with Abed and we are investigating.

    We saw this post on the E2E, it is very similar problem to that we are experiencing.  I wanted to see if you had any guidance on modifications to RR_TIMESLICE.

    https://e2e.ti.com/support/legacy_forums/embedded/linux/f/354/t/526244?tisearch=e2e-sitesearch&keymatch=kernel%25252520latency

    We can experiment but I feel some additional information would be very helpful.

    Thanks,

    Pete

  • Hi,

    Changing the RR time slice value maybe helpful. I was under the impression this might be for the SCHED_RR scheduling policy though. The post also mentions the CONFIG_HZ=100 timer frequency. You can change this if you like but I would test this extensively as changing the system time can have side effects, there are options in the kernel menuconfig under kernel features/timer frequency. TI only tests with CONFIG_HZ=100 and cannot comment on what happens when this value is changed. 

    Looking at the system description seems to be event driven which to me would suggest a SCHED_FIFO for a scheduling policy on the application. If you choose a SCHED_FIFO policy then changing the RR time slice will not matter too much.  Again I refer to the link on RT Linux for more details on scheduling policies.

    Best Regards,

    Schuyler

  • Schuyler,

    Thank you for the response.  

    As a test we did the following and checked the performance of a GPIO our application toggled every 5mS.

    1. Built an RT kernel based on 5.2
    2. Bumped our application to max priority
    3. Confirmed the CPU always running at max frequency (1GHz)
    4. As a test the thermal manager was disabled (prevent throttling)
    5. Memory locked our application for efficiency

    After each step which built upon the previous we could see from evaluation that the occurrences of delay greater than 5mS were reduced but it still is happening.  I am concerned that maybe in this brief test we do not have all parameters optimized.  Can you comment on these results?

    Pete

  • Hi,

    I am out of the office until the 12th and will respond when back. What I can recommend for the moment is to run cyclictest as a means to baseline your system performance. Make sure that you use the command line options regarding clock nanosleep and locking the memory into DDR. One note here is to not use the highest priority since this is what the system timer runs at, you don't want to compete with that. 5mS is prettly long. You mentioned that you rebuilt kernel based on 5.2, this is the TI SDK version? When installing were the rt compiled drivers installed? Could you try the TI prebuilt kernel and drivers from this SDK? 

    Best Regards,

    Schuyler

  • Hi,

    Is this still an issue?

    Were you able to baseline your system with cyclictest? If so what were the command line parameters?

    Best Regards,

    Schuyler

  • Hello Schuyler

    we were able to solve the problem. we found and eliminated the cause of the problem. 

    thank you 

    Abed