TMS320C6748: UART Error Handling

Tyler Turcotte

Part Number: TMS320C6748

I currently have an issue with my code that causes an error in the UART. The IIR INTID gives me a 011. I've been able to read the contents of the register which clears the error status caused by an overrun error per the LSR register. This is easily cleared by reading from the LSR register and that then changes the IIR INTID to 010.

Obviously the overrun is definitely an issue (Likely due to another interrupt service routine taking too long) but being able to recover from errors is important rather than the terminal just hanging. To remove the 010 interrupt condition in the IIR, the Technical reference states you just need to read from the RBR which I have done with:

HWREG(SOC_UART_2_REGS + UART_RBR);

Yet when I read from the RBR the LSR still reflects that data is ready and the IIR reflects 010.

Being only a single byte setup in the FIFO I believe that just reading from the RBR should disable the interrupt.

Am I missing something from the Technical Reference Manual?

over 6 years ago

0 Sahin Okur over 6 years ago

TI__Mastermind 27355 points

Hello,

See Table 30-11 in the TRM:

It looks like either a character needs to be written to THR or IIR needs to be read in order to clear that interrupt. Can you give that a try?

0 Tyler Turcotte over 6 years ago in reply to Sahin Okur

Prodigy 240 points

Sahin,

Even if my IIR Bits set is 010 which indicates Receiver Data Ready? I've tried to drop the FIFO level below the threshold of one byte by just reading the RBR register once which contains a byte of data. But it hasn't worked.

Tyler

0 Sahin Okur over 6 years ago in reply to Tyler Turcotte

TI__Mastermind 27355 points

Tyler,

There should be a total of 4 IIR INTID bits. Are you reading 0100 or 0010? I assumed the latter which would indicate a "Transmitter holding register empty" interrupt. Can you please clarify?

0 Tyler Turcotte over 6 years ago in reply to Sahin Okur

Prodigy 240 points

Here are some visual aids for clarification.

Upon initial error my IIR looks like this:

I then read the LSR to clear the overrun error:

HWREG(SOC_UART_2_REGS + UART_LSR);

Which indicates that there is only data left that needs to be read. I try to read using:

HWREG(SOC_UART_2_REGS + UART_RBR);

However, as you can see above the data-ready bit is still there and the interrupt has not been cleared. How, can I clear this interrupt? The technical information states you only need to read the RBR register to clear this.

0 Sahin Okur over 6 years ago in reply to Tyler Turcotte

TI__Mastermind 27355 points

Hi Tyler,

Thank you for the clarification.

It looks like you are in FIFO mode given that FIFOEN == 3, is my understanding correct?

If so, you will need to follow the guidance in Table 30-11 for FIFO mode to clear the interrupt:

0 Tyler Turcotte over 6 years ago in reply to Sahin Okur

Prodigy 240 points

Sahin,

I've checked to see the number of bytes in the register and it shows 0 bytes so therefore the interrupt should not have gone off and I can't forsee a way to clear the interrupt.

See RFIFOSTS

It seems as though there is something in the Transmit FIFO and maybe that's responsible even though it should be triggering this interrupt?

I've even had my program read the FIFO data to make sure it's been read but still it doesn't clear the interrupt.

0 Sahin Okur over 6 years ago in reply to Tyler Turcotte

TI__Mastermind 27355 points

Hi Tyler,

Could you please provide us a test case and steps to reproduce so that we can reproduce this issue on our end? Also, please indicate if you are using the LCDK or a custom board.

Regards,
Sahin

0 Sahin Okur over 6 years ago in reply to Sahin Okur

TI__Mastermind 27355 points

Tyler,

I am closing this thread for now. Please feel free to post a reply here with any updates.

Regards,
Sahin

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TMS320C6748: UART Error Handling