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RTOS/TDA2SX: Changes required for new board

ARUN KUMAR1
Intellectual 820 points
Part Number: TDA2SX


Tool/software: TI-RTOS

Hi,

I am currently building a custom board by referring to the TDA2x EVM.

I  would like to know the initial board bring up steps.

1) What all things are to be noted ?

For custom board schematic, I did pinmuxing manually in uboot (mux_data.h) and kernel device tree. Since, custom-board.pinmux file is not generating complete device tree and mux data except mmc.

2) Is there anything changes required in u-boot dts ?

3) Any Clock / PLL values need to set ?

4) Where i have to initialize VIP Ports (Uboot / Kernel) ?  Camera VIN/VOUT pins mentioned in mux_data.h.

 

Regards,

Arunkumar V N

  • 0
    TI__Genius 14650 points

    Hi Arunkumar,

    The first step is to makesure you set your pinmux configuration is set correctly. You can use the pinmux tool available below to generate the piunmux file.

    http://www.ti.com/tool/PINMUXTOOL

    The above needs to be fed to u-boot (mux_data.h generated), to ensure the changes for your custom board take effect.

    Regarding dts, yes, you may want to disable modules in the DTS which aren't present on your board. This applies to both u-boot and kernel.

    No you don't need to modify the Clock/PLL values. You can use the values set by default.

    If you use the above pinmux tool, the generated pinmux file will acount for the correct pinmux config for the VIP ports. Please note, pinmux is to be done in u-boot and not from kernel.


    Regards

    Shravan

  • 0 in reply to Shravan Karthik
    Intellectual 820 points

    Thanks Shravan for the reply,

    pinmux tool not generating complete pinmux expect mmc.

    Please verify this devictree file attached and let me know. what changes have to do to download the complete device tree from pinmux tool.

    Fullscreen 1586.devicetree.txt Download 
    /**
 * Note: This file was auto-generated by TI PinMux on 7/26/2019 at 4:16:01 PM.
 *
 * \file devicetree.txt
 *
 * \brief This file should only be used as a reference! This file contains
 *  register configuration information for the AM57xx Control Module. Two
 *  formats are provided in this file. The device tree (.dts) format WHICH 
 *  MAY CHANGE BETWEEN LINUX KERNEL VERSIONS and a generic format. For 
 *  summarization and description of the pad register bits refer to the
 *  "Control Module" chapter of the device Data Manual. This file should only
 *  be used as a reference. Some pins and/or peripherals, depending on your
 *  use case, may need additional configuration. Only MMC modes are exported
 *  here. All other pad configuration must be done by u-boot. 
 *
**/


/* * DEVICE TREE FORMAT PADCONF * */

&dra7_pmx_core {

	mmc1_pins_ds: pinmux_mmc1_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr12: pinmux_mmc1_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_ddr50: pinmux_mmc1_pins_ddr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr104: pinmux_mmc1_pins_sdr104 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_hs: pinmux_mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr25: pinmux_mmc1_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr50: pinmux_mmc1_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc2_pins_std: pinmux_mmc2_pins_std {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: pinmux_mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr: pinmux_mmc2_pins_ddr {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs200: pinmux_mmc2_pins_hs200 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

};


/* * DEVICE TREE FORMAT IODELAY * */

&dra7_iodelay_core {
// for linux kernel 4.4 / processor sdk 3.x
	mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(1076) | G_DELAY(330)) 	/* CFG_MMC1_CLK_IN */
			0x620 (A_DELAY(1271) | G_DELAY(0)) 	/* CFG_MMC1_CLK_OUT */
			0x624 (A_DELAY(722) | G_DELAY(0)) 	/* CFG_MMC1_CMD_IN */
			0x628 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OEN */
			0x62C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OUT */
			0x630 (A_DELAY(751) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_IN */
			0x634 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(20) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OUT */
			0x63C (A_DELAY(256) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_IN */
			0x640 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OUT */
			0x648 (A_DELAY(263) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_IN */
			0x64C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OUT */
			0x654 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_IN */
			0x658 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OEN */
			0x65C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(600) | G_DELAY(400)) 	/* CFG_MMC1_CLK_OUT */
			0x628 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OEN */
			0x62C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(30) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OUT */
			0x64C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OEN */
			0x65C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
		pinctrl-single,pins = <
			0x1D0 (A_DELAY(935) | G_DELAY(280)) 	/* CFG_GPMC_A23_OUT */
			0x364 (A_DELAY(684) | G_DELAY(0)) 	/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(76) | G_DELAY(0)) 	/* CFG_GPMC_CS1_OUT */
			0x1D8 (A_DELAY(621) | G_DELAY(0)) 	/* CFG_GPMC_A24_OEN */
			0x1DC (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A24_OUT */
			0x1E4 (A_DELAY(183) | G_DELAY(0)) 	/* CFG_GPMC_A25_OEN */
			0x1E8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_OUT */
			0x1F0 (A_DELAY(467) | G_DELAY(0)) 	/* CFG_GPMC_A26_OEN */
			0x1F4 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A26_OUT */
			0x1FC (A_DELAY(262) | G_DELAY(0)) 	/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(46) | G_DELAY(0)) 	/* CFG_GPMC_A27_OUT */
			0x190 (A_DELAY(274) | G_DELAY(0)) 	/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(162) | G_DELAY(0)) 	/* CFG_GPMC_A19_OUT */
			0x1A8 (A_DELAY(401) | G_DELAY(0)) 	/* CFG_GPMC_A20_OEN */
			0x1AC (A_DELAY(73) | G_DELAY(0)) 	/* CFG_GPMC_A20_OUT */
			0x1B4 (A_DELAY(465) | G_DELAY(0)) 	/* CFG_GPMC_A21_OEN */
			0x1B8 (A_DELAY(115) | G_DELAY(0)) 	/* CFG_GPMC_A21_OUT */
			0x1C0 (A_DELAY(633) | G_DELAY(0)) 	/* CFG_GPMC_A22_OEN */
			0x1C4 (A_DELAY(47) | G_DELAY(0)) 	/* CFG_GPMC_A22_OUT */
		>;
	};

};



/* * GENERIC FORMAT PADCONF * */

	/* MMC1_PINS_DS */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR12 */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_DDR50 */
	0x1754	0x60100	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60100	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60100	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60100	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60100	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60100	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR104 */
	0x1754	0x60100	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60100	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60100	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60100	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60100	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60100	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_HS */
	0x1754	0x601B0	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x601B0	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x601B0	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x601B0	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x601B0	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x601B0	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR25 */
	0x1754	0x601B0	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x601B0	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x601B0	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x601B0	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x601B0	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x601B0	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR50 */
	0x1754	0x601A0	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x601A0	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x601A0	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x601A0	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x601A0	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x601A0	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC2_PINS_STD */
	0x149C	0x60001	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60001	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60001	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60001	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60001	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60001	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60001	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60001	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60001	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60001	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_HS */
	0x149C	0x60001	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60001	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60001	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60001	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60001	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60001	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60001	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60001	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60001	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60001	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_DDR */
	0x149C	0x60001	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60001	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60001	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60001	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60001	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60001	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60001	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60001	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60001	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60001	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_HS200 */
	0x149C	0x60101	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60101	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60101	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60101	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60101	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60101	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60101	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60101	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60101	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60101	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7


/* * GENERIC FORMAT IODELAY * */

	/* MMC1_IODELAY_DDR50 */
	0x618	1076	330	CFG_MMC1_CLK_IN	W6
	0x620	1271	0	CFG_MMC1_CLK_OUT	W6

	0x624	722	0	CFG_MMC1_CMD_IN	Y6
	0x628	0	0	CFG_MMC1_CMD_OEN	Y6
	0x62C	0	0	CFG_MMC1_CMD_OUT	Y6

	0x630	751	0	CFG_MMC1_DAT0_IN	AA6
	0x634	0	0	CFG_MMC1_DAT0_OEN	AA6
	0x638	20	0	CFG_MMC1_DAT0_OUT	AA6

	0x63C	256	0	CFG_MMC1_DAT1_IN	Y4
	0x640	0	0	CFG_MMC1_DAT1_OEN	Y4
	0x644	0	0	CFG_MMC1_DAT1_OUT	Y4

	0x648	263	0	CFG_MMC1_DAT2_IN	AA5
	0x64C	0	0	CFG_MMC1_DAT2_OEN	AA5
	0x650	0	0	CFG_MMC1_DAT2_OUT	AA5

	0x654	0	0	CFG_MMC1_DAT3_IN	Y3
	0x658	0	0	CFG_MMC1_DAT3_OEN	Y3
	0x65C	0	0	CFG_MMC1_DAT3_OUT	Y3

	/* MMC1_IODELAY_SDR104 */
	0x620	600	400	CFG_MMC1_CLK_OUT	W6

	0x628	0	0	CFG_MMC1_CMD_OEN	Y6
	0x62C	0	0	CFG_MMC1_CMD_OUT	Y6

	0x634	0	0	CFG_MMC1_DAT0_OEN	AA6
	0x638	30	0	CFG_MMC1_DAT0_OUT	AA6

	0x640	0	0	CFG_MMC1_DAT1_OEN	Y4
	0x644	0	0	CFG_MMC1_DAT1_OUT	Y4

	0x64C	0	0	CFG_MMC1_DAT2_OEN	AA5
	0x650	0	0	CFG_MMC1_DAT2_OUT	AA5

	0x658	0	0	CFG_MMC1_DAT3_OEN	Y3
	0x65C	0	0	CFG_MMC1_DAT3_OUT	Y3

	/* MMC2_IODELAY_HS200 */
	0x1D0	935	280	CFG_GPMC_A23_OUT	J7

	0x364	684	0	CFG_GPMC_CS1_OEN	H6
	0x368	76	0	CFG_GPMC_CS1_OUT	H6

	0x1D8	621	0	CFG_GPMC_A24_OEN	J4
	0x1DC	0	0	CFG_GPMC_A24_OUT	J4

	0x1E4	183	0	CFG_GPMC_A25_OEN	J6
	0x1E8	0	0	CFG_GPMC_A25_OUT	J6

	0x1F0	467	0	CFG_GPMC_A26_OEN	H4
	0x1F4	0	0	CFG_GPMC_A26_OUT	H4

	0x1FC	262	0	CFG_GPMC_A27_OEN	H5
	0x200	46	0	CFG_GPMC_A27_OUT	H5

	0x190	274	0	CFG_GPMC_A19_OEN	K7
	0x194	162	0	CFG_GPMC_A19_OUT	K7

	0x1A8	401	0	CFG_GPMC_A20_OEN	M7
	0x1AC	73	0	CFG_GPMC_A20_OUT	M7

	0x1B4	465	0	CFG_GPMC_A21_OEN	J5
	0x1B8	115	0	CFG_GPMC_A21_OUT	J5

	0x1C0	633	0	CFG_GPMC_A22_OEN	K6
	0x1C4	47	0	CFG_GPMC_A22_OUT	K6

    Regards

    ARUNKUMAR

  • 0 in reply to ARUN KUMAR1
    TI__Genius 9905 points

    Hi,

    As part of the IOdelay errata workaround, TI recommends to perform all of the pinmux and iodelay configuration from first stage bootloader for all peripherals except MMC to gurantee timings.

    Therefore, your changes to u-boot mux_data,h and for kernel dts with MMC nodes are sufficient, you dont need anything else

    Regards,

    Nikhil D