• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 97 subscribers
  • Views 224 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: Cache

Nancy Wang
Expert 8210 points
Part Number: TMS320C6678

Hi,

The customer write data to 0x80010000 from FPGA to DSP by SRIO. Then DSP copy data from 0x80010000 to 0x90000000 by memcpy. But the data wrong unless he used CACHE_invL1d() in 0x80010000. His DDR3 is non-cacheable. Please help explain in detail.

  • 0
    TI__Guru* 95265 points

    Hi,

    I don't think this can happen if DDR is non-cacheable. Please provide MAR register dump for the whole DDR region. That is MAR128 to MAR255. (Register 0184 8200h to  0184 83FCh). Or, please confirm the setting of MAR128 and MAR144. Each region is 16MB.

    Regards, Eric