Hi,
I was trying to configure spi1 on AMIC110.
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Hi,
I was trying to configure spi1 on AMIC110.
Hi,
Please refer to section 24.3.11 in the AM335x TRM Rev. P for correct programming sequence.
Orient,
I am closing the thread as the issue has been resolved with local FAE's help...
Regards,
Garrett
Hi,Garrett
The problem was solved by adding a read operation for MCSPI_TX[i] or MCSPI_RX[i] register. Without using a fifo, this extra operation must be done or there will be no response from signal pins. It seem the spruh73p manual did not describe this extra step clearly.
Kind regards
Orient
Hi Garrett,
The FIFO is enabled. Data was written continually to MCSPI_TX0. There was only 1 FIFO cycle with 8 words of transfer. The CH0STAT was showwing TXS = 1, EOT = 1, RXS = 1, TXFFF = 1; How to continual transfer data?
Kind regards
Orient
Orient,
Did you connect a SPI analyzer to check if the 32-byte data is transmitted to the wire successfully? Make sure you have clock, polarity, phase set up correctly in both SPI master and slave.
Additionally, you can refer to tiesc_spi_slave.c for raw register level SPI tx/rx API, which is close to what you are trying to test.
Regards,
Garrett
Hi Garrett,
The spi wiring was verified by baremetal program. I also had C2000 program to receive data.
Detail of data transfer was interesting. The test program was continually writing uint16 variable to TX0 register. TX0 register was written 32 times with before TXFFF setting to 1. C2000 could only receive 8 set of uint16 variable transferred from SPI master. Then data transfer was halted when TXFFF = 1.
It took me a while to solve this problem. For continual data transfer, the TXFFF from CH0STAT was cleared by re-enable the channel with EN bit from CH0CTRL. This operation could lead to gaps between each 8 sets of data. Do you have better ideas?
Kind regards
Orient
Orient,
C2000 (F2837xd) FIFO is 16 word depth, which should allow you receive 16 sets of uint16 variable transferred from SPI master. You should try to send the same amount of data and check the available FIFO buffers then transmit more data...
Regards,
Garrett