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TMS320C6678: Board reset to run new thernet configuration

Part Number: TMS320C6678

I have a client program, running on core0, that has a defined static IP address that allows socket connection with a host PC.

It runs through some Stacktest-like code from the NIMU-emacClientSockets example and outputs a trace:

"Network Added: If-1:10.10.251.50". The socket works well.

I want to send a new program via socket to reboot onto core0 that can also provide a client - socket connection,

but I am unclear what has to be done to kill off (Shutdown?)the old connection and allow the new task to run the stacktest configuration code.

Can I do a SOFTRESET, of some kind, to reinitialise the ethernet so that the new task can start from scratch to connect to the PC?

I can reboot to the new task but I can't get it to produce the

"Network Added: If-1:10.10.251.50". trace.

  • Hi Eric,

    I have followed the trail of suggested posts with no real success.

    I need to be able programmatically to reset the ethernet subsystem from core0 on the standard dev board TMDSEVM6678LE

    which can only be achieved at the moment by manually resetting the board.

    In one of the replies the EVM_init routine, included below, is proposed as a 'soft' reset, and in the

    0246.client_6678_restart_test it seems to have a beneficial effect.

    I have an application that sets up a static IP for connection to a single socket on the host PC

    and it uses the EVM_init routine; at every restart it will produce the following trace:

    Network Added: If-1:10.10.251.50 (from NetworkIPAddr() callback when the stack signals an ip address change)

    this is good since it seems to suggest a new stack has been launched.

    If I implant the same code into the Nimu_emacClientSockets example I don't get the same effect;

    it gets stuck in the setDomainAndModulePower call - won't transition the power

    looping round at while(!CSL_PSC_isStateTransitionDone (domain));

    Can you shed some light on to this behaviour?

    Regards,

    Jack

    void EVM_init()

    {
        platform_init_flags     sFlags;
        platform_init_config    sConfig;
        /* Status of the call to initialize the platform */
        int32_t pform_status;

        /* Disabling PA PDSP to prepare for power down */
        volatile unsigned int *passPDSP;
        passPDSP = (unsigned int*)PASS_PDSP0;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP1;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP2;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP3;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP4;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP5;
        *passPDSP &= 0xFFFFFFFD;
        /* Turning off the NetCP modules and domain */
        setModulePower(CSL_PSC_LPSC_CPGMAC, CSL_PSC_PD_PASS, 0);
        setModulePower(CSL_PSC_LPSC_Crypto, CSL_PSC_PD_PASS, 0);
        setDomainAndModulePower(CSL_PSC_LPSC_PKTPROC, CSL_PSC_PD_PASS, 0);

        /*
         * You can choose what to initialize on the platform by setting the following
         * flags. Things like the DDR, PLL, etc should have been set by the boot loader.
        */
        memset( (void *) &sFlags,  0, sizeof(platform_init_flags));
        memset( (void *) &sConfig, 0, sizeof(platform_init_config));

        sFlags.pll  = 0;    /* PLLs for clocking    */
        sFlags.ddr  = 0;    /* External memory      */
        sFlags.tcsl = 1;    /* Time stamp counter   */
    #ifdef _SCBP6618X_
        sFlags.phy  = 0;    /* Ethernet             */
    #else
        sFlags.phy  = 1;    /* Ethernet             */
    #endif
        sFlags.ecc  = 0;    /* Memory ECC           */

        sConfig.pllm = 0;   /* Use libraries default clock divisor */

        pform_status = platform_init(&sFlags, &sConfig);

        /* If we initialized the platform okay */
        if (pform_status != Platform_EOK) {
            /* Initialization of the platform failed... die */
            while (1) {
                (void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
                (void) platform_delay(50000);
                (void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
                (void) platform_delay(50000);
            }
        }
    }

    void setDomainAndModulePower(unsigned int module, unsigned int domain, unsigned int state)
    {
        while(!CSL_PSC_isStateTransitionDone (domain));

        if(state)
        {
            CSL_PSC_enablePowerDomain(domain);
            CSL_PSC_setModuleNextState(module, PSC_MODSTATE_ENABLE );
        }
        else
        {
            CSL_PSC_disablePowerDomain(domain);
            CSL_PSC_setModuleNextState(module, PSC_MODSTATE_SWRSTDISABLE );
        }

        CSL_PSC_startStateTransition(domain);

        while(!CSL_PSC_isStateTransitionDone (domain));

        return;
    }

    /** ============================================================================
     *   @n@b setModulePower
     *
     *   @b Description
     *   @n This function sets the power for a module
     *
     *   @b Arguments
     *   @verbatim
            module          Module for which the power is being set
            domain          Domain for which the power is being set
            state           Next state to which the module will be transitioned.
         @endverbatim
     *
     *   <b> Return Value </b>  None
     *
     *   <b> Pre Condition </b>
     *   @n  None
     *
     *   <b> Post Condition </b>
     *   @n  Module is moved to the state described by the state parameter
     *
     *   @b  Example
     *   @verbatim
            ...
            // Disable the SRIO's power module
            setModulePower(CSL_PSC_LPSC_SRIO, 0);
            ...
         @endverbatim
     * ============================================================================
     */
    void setModulePower(unsigned int module, unsigned int domain, unsigned int state)
    {
        while(!CSL_PSC_isStateTransitionDone (domain));

        if(state)
            CSL_PSC_setModuleNextState(module, PSC_MODSTATE_ENABLE );
        else
            CSL_PSC_setModuleNextState(module, PSC_MODSTATE_SWRSTDISABLE );

        CSL_PSC_startStateTransition(domain);

        while(!CSL_PSC_isStateTransitionDone (domain));

        return;
    }

  • Hi,

    I don't see you power on the PSC domain, so I assume you had power state transition stuck on the power off. There are sequences to power off and power on, you can refer to the pdk_c667x_2_0_13\packages\ti\boot\examples\pcie\linux_host_loader\pciedemo.c

    The power off:

    setPscState(PD2, LPSC_SA, PSC_SWRSTDISABLE);
    setPscState(PD2, LPSC_SGMII, PSC_SWRSTDISABLE);
    setPscState(PD2, LPSC_PA, PSC_SWRSTDISABLE);

    Then power on:

    setPscState(PD2, LPSC_PA, PSC_ENABLE);
    setPscState(PD2, LPSC_SGMII, PSC_ENABLE);
    setPscState(PD2, LPSC_SA, PSC_ENABLE);

    Regards, Eric

  • Hi Eric,

    the setPscState example that you refer to seems to act over PCIE from a linux core,

    but I'm running this code in core0 of the c6678,

    so I've converted the routines to reflect this; its writing to registers in the PSC block starting at 0x2350000

    I include a conversion in setPscStateX routine below.

    It doesn't seem to run successfully giving :

    MD stat for pid 2 mid 9 state: 0 timeout
    MD stat for pid 2 mid 8 state: 0 timeout
    MD stat for pid 2 mid 7 state: 0 timeout
    MD stat for pid 2 mid 7 state: 3 timeout
    MD stat for pid 2 mid 8 state: 3 timeout
    MD stat for pid 2 mid 9 state: 3 timeout

    can you shed any further light on this reset issue and whether this approach has a good chance of  yielding results?

    Is it possible to debug the EVM_init routine line by line checking the progress of the initialisation?

    void EVM_init()
    {
        HwKick();
        platform_init_flags      sFlags;
        platform_init_config     sConfig;
        /* Status of the call to initialize the platform */
        int32_t pform_status;

        /* Disabling PA PDSP to prepare for power down */
        volatile unsigned int *passPDSP;
        passPDSP = (unsigned int*)PASS_PDSP0;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP1;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP2;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP3;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP4;
        *passPDSP &= 0xFFFFFFFD;

        passPDSP = (unsigned int*)PASS_PDSP5;
        *passPDSP &= 0xFFFFFFFD;

        //The power off:

        setPscStateX(PD2, LPSC_SA, PSC_SWRSTDISABLE);
        setPscStateX(PD2, LPSC_SGMII, PSC_SWRSTDISABLE);
        setPscStateX(PD2, LPSC_PA, PSC_SWRSTDISABLE);

        //Then power on:

        setPscStateX(PD2, LPSC_PA, PSC_ENABLE);
        setPscStateX(PD2, LPSC_SGMII, PSC_ENABLE);
        setPscStateX(PD2, LPSC_SA, PSC_ENABLE);

        /* Turning off the NetCP modules and domain */
        setModulePower(CSL_PSC_LPSC_CPGMAC, CSL_PSC_PD_PASS, 0);
        setModulePower(CSL_PSC_LPSC_Crypto, CSL_PSC_PD_PASS, 0);
        setDomainAndModulePower(CSL_PSC_LPSC_PKTPROC, CSL_PSC_PD_PASS, 0);


        //setPscStateX(PD2, LPSC_SA, PSC_SWRSTDISABLE);

        // new setPscState(PD2, LPSC_SA, PSC_SWRSTDISABLE);// new
        /*
         * You can choose what to initialize on the platform by setting the following
         * flags. Things like the DDR, PLL, etc should have been set by the boot loader.
        */
        memset( (void *) &sFlags,  0, sizeof(platform_init_flags));
        memset( (void *) &sConfig, 0, sizeof(platform_init_config));

        sFlags.pll  = 0;    /* PLLs for clocking      */
        sFlags.ddr  = 0;       /* External memory         */
        sFlags.tcsl = 1;    /* Time stamp counter     */
    #ifdef _SCBP6618X_
        sFlags.phy  = 0;    /* Ethernet             */
    #else
        sFlags.phy  = 1;    /* Ethernet             */
    #endif
          sFlags.ecc  = 0;    /* Memory ECC             */

        sConfig.pllm = 0;    /* Use libraries default clock divisor */

        pform_status = platform_init(&sFlags, &sConfig);

        /* If we initialized the platform okay */
        if (pform_status != Platform_EOK) {
            /* Initialization of the platform failed... die */
            while (1) {
                (void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
                (void) platform_delay(50000);
                (void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
                (void) platform_delay(50000);
            }
        }
    }

    /* PSC registers */
    #define PSC_BASE_ADDRESS             0x02350000
    #define PTCMD                        0x120
    #define PTSTAT                       0x128
    #define PDSTAT(n)                    (0x200 + (4 * (n)))
    #define PDCTL(n)                     (0x300 + (4 * (n)))
    #define MDSTAT(n)                    (0x800 + (4 * (n)))
    #define MDCTL(n)                     (0xA00 + (4 * (n)))

    void setPscStateX(uint32_t pid, uint32_t mid, uint32_t state)
    {
        uint32_t *pReg, mdctl, pdctl, temp, counter = 0;

        /* Point to PCIE application registers */
    //?    pReg = (uint32_t *)regVirt;
        /* Set MST_PRIV bit to access PSC via PCIE */
    //?    iowrite32(((ioread32(pReg + PRIORITY/4))|0x00010000), pReg + PRIORITY/4);

        /* Temporarily re-map IB region 3 from DDR memory to PSC registers */
    //?    iowrite32(PSC_BASE_ADDRESS, pReg + IB_OFFSET(3)/4);
        /* Now it points to the start of PSC_BASE_ADDRESS */
    //?    pReg = (uint32_t*)ddrVirt;
        pReg = (uint32_t*)PSC_BASE_ADDRESS;


    //?    mdctl = myIoread32(pReg + MDCTL(mid)/4);
    //?    pdctl = myIoread32(pReg + PDCTL(pid)/4);
        pReg = (uint32_t*)(PSC_BASE_ADDRESS + MDCTL(mid)/4);
        mdctl = *pReg;

        pReg = (uint32_t*)(PSC_BASE_ADDRESS + PDCTL(pid)/4);
        pdctl = *pReg;

        /* No previous transition in progress */
        counter = 0;
        while (true) {

    //?        temp = myIoread32(pReg + PTSTAT/4);
            pReg = (uint32_t*)(PSC_BASE_ADDRESS + PTSTAT/4);
            temp = *pReg;
            if ((temp & (1 << pid)) == 0) break;
            mdelayX(1);
            counter ++;
            if (counter > 10) {
                printf("Previous transition in progress pid %d mid %d state: %d\n", pid, mid, state);
                break;
            }
        }

        /* Set power domain control */
    //?    myIowrite32(pdctl | 0x1, pReg + PDCTL(pid)/4);
        pReg = (uint32_t*)(PSC_BASE_ADDRESS + PDCTL(pid)/4);
        *pReg = pdctl | 0x1;
        /* Set MDCTL NEXT to new state */
        mdctl = ((mdctl) & ~(0x1f)) | state;
    //?    myIowrite32(mdctl, pReg + MDCTL(mid)/4);
        pReg = (uint32_t*)(PSC_BASE_ADDRESS + MDCTL(mid)/4);
        *pReg = mdctl;

        /* Start power transition by setting PTCMD GO to 1 */
    //?    temp = myIoread32(pReg + PTCMD/4);
        pReg = (uint32_t*)(PSC_BASE_ADDRESS + PTCMD/4);
        temp = *pReg;

    //?    myIowrite32(temp | (0x1<<pid), pReg + PTCMD/4);
        pReg = (uint32_t*)(PSC_BASE_ADDRESS + PTCMD/4);
        *pReg = temp | (0x1<<pid);

        /* Current transition finished */
        counter = 0;
        while (true) {
    //?        temp = myIoread32(pReg + PTSTAT/4);
            pReg = (uint32_t*)(PSC_BASE_ADDRESS + PTSTAT/4);
            temp = *pReg;

            if ((temp & (1 << pid)) == 0) break;
            mdelayX(1);
            counter ++;
            if (counter > 10) {
                printf("Current transition in progress pid %d mid %d state: %d\n", pid, mid, state);
                break;
            }
        }

        /* Verifying state change */
        counter = 0;
        while (true) {
    //?        temp = myIoread32(pReg + MDSTAT(mid)/4);
            pReg = (uint32_t*)(PSC_BASE_ADDRESS + MDSTAT(mid)/4);
            temp = *pReg;

            if ((temp & 0x1F) == state) break;
            mdelayX(1);
            counter ++;
            if (counter > 10) {
                printf("MD stat for pid %d mid %d state: %d timeout\n", pid, mid, state);
                break;
            }
        }

        /* Restore pointer */
    //?    pReg = (uint32_t *)regVirt;     /* Point to PCIE application registers */
    //?    iowrite32(DDR_START, pReg + IB_OFFSET(3)/4);
    }

  • Hi,

    I wrote a small CCS project to turn off Ethernet then turn it on, I didn't see any problem. It runs on core 0, you can step through the code and look at the value change on 0x235_0800, offset 0x1c and 0x20 from CCS memory window.

    After GEL initialization: both are 0x1F03. Then I turned them off: both are 0xA00. Then I turn them on again: both are 0x1F03. I didn't get any stuck on transition.

    Note the code is just my testing code FYI, not TI official one for production. C66_PSC.zip

    Regards, Eric

  • Hi,

    Initially I get the same results when using your code section; I can see the memory locations changing as you say.

    I can step through the routine with no blocking, then restart the program and repeat the routine again.

    When I continue to do further ethernet peripheral init for qmss, cppi all seems well until the packet accelerator init is done

    in the routine Nimu_testInitPASS()   -> Download_PAFirmware().

    If I breakpoint at Download_PaFirmware and then reload and start the program again I see no timeout problems

    but if I run through Download_PaFirmware timeout problems occur on restart;

    a manual reset is needed to correct the problem.

    I seems that some further init. of the PA peripherals is needed to achieve the desired soft reset .

    The code exits Nimu_testInitPASS() stating that the PA is successfully initialised but restart is problematic.

    What do you think?

    Regards,

    Jack

  • Jack,

    "n the routine Nimu_testInitPASS()   -> Download_PAFirmware().

    If I breakpoint at Download_PaFirmware and then reload and start the program again I see no timeout problems

    but if I run through Download_PaFirmware timeout problems occur on restart;"

    I checked the discussion and didn't see the code Nimu_testInitPASS()   -> Download_PAFirmware(). you mentioned? Can you point me where it is?

    Regards, Eric

  • Hi Eric,

    sorry for the confusion;

    Nimu_testInitPASS call should be : res_mgr_init_pass (see below)

    Jack

    /**********************************************************************
     ************ Resource Manager PA configuration Functions ************
     **********************************************************************/
    /** ============================================================================
     *   @n@b Download_PAFirmware
     *
     *   @b Description
     *   @n This API downloads the PA firmware required for PDSP operation.
     *
     *   @param[in]
     *   @n None
     *
     *   @return    int32_t
     *              -1      -   Error
     *              0       -   Success
     * =============================================================================
     */
    static int32_t Download_PAFirmware (Void)
    {
        int32_t                   i;

        /* Hold the PA in reset state during download */
        Pa_resetControl (gPAInstHnd, pa_STATE_RESET);

        /* PDPSs 0-2 use image c1 */
        for (i = 0; i < 3; i++)
        {
            Pa_downloadImage (gPAInstHnd, i, (Ptr)c1, sizeof(c1));
        }

        /* PDSP 3 uses image c2 */
        Pa_downloadImage (gPAInstHnd, 3, (Ptr)c2, sizeof(c2));

        /* PDSPs 4-5 use image m */
        for (i = 4; i < 6; i++)
        {
            Pa_downloadImage (gPAInstHnd, i, (Ptr)m, sizeof(m));
        }

        /* Enable the PA back */
        Pa_resetControl (gPAInstHnd, pa_STATE_ENABLE);

        return 0;
    }

    /* ============================================================================
     *   @n@b res_mgr_init_pass
     *
     *   @b Description
     *   @n This API initializes the PASS/PDSP.
     *
     *   @param[in]
     *   @n None
     *
     *   @return    int32_t
     *              -1      -   Error
     *              0       -   Success
     * =============================================================================
     */

    int32_t
    res_mgr_init_pass
    (
        void
    )
    {
        paSizeInfo_t                paSize = {0};
        paConfig_t                  paCfg = {0};
        int32_t                     retVal;
        int32_t                     sizes[pa_N_BUFS];
        int32_t                     aligns[pa_N_BUFS];
        void*                       bases[pa_N_BUFS];
        
        /* Allocate space for the PA LLD buffers. The buffers we need to
        * allocate space are:
        *      (1) PA LLD Instance Info Handle
        *      (2) PA LLD L2 Handle database
        *      (3) PA LLD L3 Handle database
        */
        paSize.nMaxL2 = MAX_NUM_L2_HANDLES;
        paSize.nMaxL3 = MAX_NUM_L3_HANDLES;
        if ((retVal = Pa_getBufferReq(&paSize, sizes, aligns)) != pa_OK)
        {
            platform_write ("Pa_getBufferReq returned error %d\n", retVal);
            return -1;
        }
        
        /* Validate the buffer allocations */
        /* The first buffer is always the instance buffer */
        if ((uint32_t)gPAInst & (aligns[0] - 1))
        {
            platform_write("Pa_getBufferReq requires %d alignment for instance buffer, but address is 0x%08x\n", aligns[0], (uint32_t)gPAInst);
            return -1;
        }
        
        if (sizeof(gPAInst) < sizes[0])
        {
            platform_write ("Pa_getBufferReq requires %d bytes for instance buffer, have only %d\n", sizes[0], sizeof(gPAInst));
            return -1;
        }
        
        bases[0]    =   (Void *)gPAInst;
        
        /* The second buffer is the L2 table */
        if ((uint32_t)gMemL2Ram & (aligns[1] - 1))
        {
            platform_write ("Pa_getBufferReq requires %d alignment for buffer 1, but address is 0x%08x\n", aligns[1], (uint32_t)gMemL2Ram);
            return (-1);
        }
        
        if (sizeof(gMemL2Ram) < sizes[1])
        {
            platform_write ("Pa_getBufferReq requires %d bytes for buffer 1, have only %d\n", sizes[1], sizeof(gMemL2Ram));
            return -1;
        }
        
        bases[1]    =   (Void *)gMemL2Ram;
        
        /* The third buffer is the L3 table */
        if ((uint32_t)gMemL3Ram & (aligns[2] - 1))
        {
            platform_write ("Pa_alloc requires %d alignment for buffer 1, but address is 0x%08x\n", aligns[2], (uint32_t)gMemL3Ram);
            return (-1);
        }
        
        if (sizeof(gMemL3Ram) < sizes[2])
        {
            platform_write ("Pa_alloc requires %d bytes for buffer 1, have only %d\n", sizes[2], sizeof(gMemL3Ram));
            return (-1);
        }
        
        bases[2]    =   (Void *)gMemL3Ram;
        
        /* Finally initialize the PA LLD */
        paCfg.initTable =   TRUE;
        paCfg.initDefaultRoute = TRUE;
    #if defined(DEVICE_K2H) || defined(DEVICE_K2K)
        paCfg.baseAddr = CSL_NETCP_CFG_REGS;
    #else
        paCfg.baseAddr = CSL_PA_SS_CFG_REGS;
    #endif
        paCfg.sizeCfg   =   &paSize;
        if ((retVal = Pa_create (&paCfg, bases, &gPAInstHnd)) != pa_OK)
        {
            platform_write ("Pa_create returned with error code %d\n", retVal);
            return -1;
        }

    #ifdef _NO_SKIP
    #endif
        /* Download the PASS PDSP firmware */
        if (Download_PAFirmware ())
        {
            return -1;
        }
        
        /* PA Init Done. Return success */
        return 0;
    }


  • Hi,

    I tested the pdk_c667x_2_0_13\packages\MyExampleProjects\PA_emacExample_evmc6678_C66BiosExampleProject by adding code to turn off/on PA, SGMII after firmware download. I saw the issue that PA can't be turned off. I will update you what I found.

    Regards, Eric

  • Hi,

    Before turning the PA off using PSC code, you need to put PA into reset by calling    Pa_resetControl (gPAInstHnd, pa_STATE_RESET); Attached is my test code based on pdk_c667x_2_0_13\packages\MyExampleProjects\PA_emacExample_evmc6678_C66BiosExampleProject, there is one file I changed: cpsw_singlecore.c.

    At the end of the code, I have

    #ifdef PSC_TEST
    extern Pa_Handle gPAInstHnd;
    Pa_resetControl (gPAInstHnd, pa_STATE_RESET);
    mainPSC();
    #endif

    /* Example application done. Return success */
    APP_exit (0);

    where mainPSC() is contained in the main.c file.

    Regards, Eric

    /**  
     * @file cpsw_singlecore.c
     *
     * @brief 
     *  Example to illustrate the usage of EMAC CPSW3G switch using CPPI, QMSS
     * 	low level drivers and CSL.
     *
     * 	This example application does the following:
     * 	    (1) Initializes:
     * 	            (a) Queue Manager (QM) Subsystem 
     * 	            (b) Packet Accelerator (PA) CPPI DMA 
     * 	            (c) Ethernet Subsystem (Ethernet switch + SGMII + MDIO) - (Note: Applicable only for NO_BOOT mode)
     * 	            (d) PA Subsystem + PDSP - (Note: PDSP is initialized only during NO_BOOT mode)
     *
     * 	    (2) Sets up the CPPI descriptors and Queues required for sending and
     * 	        receiving data using Ethernet.
     * 	            (a) Uses Host descriptors
     * 	            (b) Uses High Priority Accumulation interrupts
     *
     * 	    (3) Sets up the example application's configuration (MAC address
     * 	        it uses to send/recv data; IP address and port number it's listening
     * 	        on) in PA Subsystem so as to enable the PASS to forward all packets
     * 	        matching this configuration onto the application for processing.
     * 	            (a) Switch MAC address configured   =   0x10:0x11:0x12:0x13:0x14:0x15
     * 	            (b) Example's IP address            =   192.168.1.10
     * 	            (c) Example App's listening port    =   0x5678
     *
     * 	    (4) Sends packets onto wire 
     * 	        (constructed manually in code here with following settings):
     * 	            (a) Source MAC      =   0x00:0x01:0x02:0x03:0x04:0x05
     * 	                Destination MAC =   0x10:0x11:0x12:0x13:0x14:0x15
     *              (b) Source IP       =   192.168.1.1
     *                  Destination IP  =   192.168.1.10
     *              (c) Source Port     =   0x1234
     *                  Destination Port=   0x5678
     *              (d) Payload Data (80 bytes)
     *
     *          The packets sent by the application are sent onto wire and 
     *          since the destination MAC on the packet is the Ethernet Switch 
     *          MAC address, the packets are received by simulator and passed 
     *          back up to the example application for processing.
     *      
     *      (5) Application receives all packets using QM High priority interrupt
     *          registered; Validates received packet against data sent.
     *
     *  Example application Setup:
     *
     *          PC Running Simulator using CCS connected to a
     *          Switch/Hub. You could put another PC on the Hub to observe packets 
     *          being sent onto wire. 
     *
     *          Please consult the Readme.txt packaged with the example to 
     *          setup the CCS simulator configuration required to run this example 
     *          succesfully.
     *
     *  \par
     *  ============================================================================
     *  @n   (C) Copyright 2009, Texas Instruments, Inc.
     * 
     *  Redistribution and use in source and binary forms, with or without 
     *  modification, are permitted provided that the following conditions 
     *  are met:
     *
     *    Redistributions of source code must retain the above copyright 
     *    notice, this list of conditions and the following disclaimer.
     *
     *    Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the 
     *    documentation and/or other materials provided with the   
     *    distribution.
     *
     *    Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
     *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
     *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
     *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
     *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
     *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
     *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
     *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
    */
    #include <cpsw_singlecore.h>
    #include <stdio.h>
    
    /**************************************************************
    ************************** DEFINITIONS ************************
    ***************************************************************/
    /* Number of packets to be used for testing the example. */
    #define                     MAX_NUM_PACKETS                         100u
    
    #define                     MAX_RETRIES                             20u
    
    /* Counters to track number of packets sent/received by this application */
    extern volatile uint32_t				gRxCounter, gTxCounter;
    
    /*
     * Default test configuration for the silicon
     *
     * To run test at the CCS simulator
     *    cpswSimTest = 1
     *    cpswLpbkMode = CPSW_LOOPBACK_INTERNAL
     */
    #ifdef  SIMULATOR_SUPPORT
    int cpswSimTest = 1;
    int cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;
    #else
    int cpswSimTest = 0;
    #ifndef __LINUX_USER_SPACE
    int cpswLpbkMode = CPSW_LOOPBACK_NONE;
    #endif
    #endif
    
    void mdebugHaltPdsp (int pdspNum);
    volatile int mdebugWait = 1;
    
    #ifdef __LINUX_USER_SPACE
    uint32_t no_bootMode = FALSE;
    /* Linux Specific global variables per process */
    sock_h                      rmClientSocket;
    sem_t                       mutex;
    #else
    uint32_t no_bootMode = TRUE;
    #endif
    
    /**************************************************************
    **************** EXAMPLE APP FUNCTIONS ************************
    ***************************************************************/
    
    /** ============================================================================
     *   @n@b Cpsw_SingleCoreApp
     *
     *   @b Description
     *   @n Example application that sets up the application, sends, receives
     *      data.
     *
     *   @param[in]  
     *   @n None
     * 
     *   @return
     *   @n None
     *
     * =============================================================================
     */
    #define PSC_TEST
    
    #ifndef __LINUX_USER_SPACE
    static  CSL_CPSW_STATS  stats [CSL_CPSW_NUMSTATBLOCKS];
    #endif
    
    #ifdef __LINUX_USER_SPACE
    void* Cpsw_SingleCoreApp (void *args)
    #else
    void Cpsw_SingleCoreApp (void)
    #endif
    {
    	extern uint32_t gNum_Mac_Ports;
    	extern void view_ale_table(void);
    	uint32_t  			i;
    	int				ct_show_ale = 0;
        int             fPass = 1;
    
        System_printf ("**************************************************\n");
        System_printf ("******* Ethernet Single Core Example Start *******\n");
        System_printf ("**************************************************\n");
        System_flush();
    
    #if RM
        if (setupRm ())
        {
          System_printf ("Function setupRm failed\n");
          System_flush();
          APP_exit (-1);
        }
    #endif
        /* Initialize the components required to run the example:
         *  (1) QMSS
         *  (2) CPPI
         *  (3) Ethernet switch subsystem + MDIO + SGMII
         */
        
        /* Initialize QMSS */
        if (Init_Qmss () != 0)
        {
            System_printf ("QMSS init failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("QMSS successfully initialized \n");
            System_flush();
        }
    
        /* Initialize CPPI */
        if (Init_Cppi () != 0)
        {
            System_printf ("CPPI init failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("CPPI successfully initialized \n");
            System_flush();
        }
    
        /* Init PA LLD */
        if (Init_PASS () != 0)
        {
            System_printf ("PASS init failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("PASS successfully initialized \n");
            System_flush();
        }
    #ifndef __LINUX_USER_SPACE
        if (no_bootMode == TRUE)
        {
            /* Initialize the CPSW switch */
            if (Init_Cpsw () != 0)
            {
                System_printf ("Ethernet subsystem init failed \n");
                System_flush();
                APP_exit (-1);
            }
            else
            {
                System_printf ("Ethernet subsystem successfully initialized \n");
                System_flush();
            }
        }
    #endif
    
        /* Setup Tx */
        if (Setup_Tx () != 0)
        {
            System_printf ("Tx setup failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("Tx setup successfully done \n");
            System_flush();
        }
    
        /* Setup Rx */
        if (Setup_Rx () != 0)
        {
            System_printf ("Rx setup failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("Rx setup successfully done \n");
            System_flush();
        }
    
        /* Setup PA */
        if (Setup_PASS () != 0)
        {
            System_printf ("PASS setup failed \n");
            System_flush();
            APP_exit (-1);
        }
        else
        {
            System_printf ("PASS setup successfully done \n");
            System_flush();
        }
    
        if (no_bootMode == TRUE)
        {
            System_printf("Following is the ALE table before transmits.\n");
            view_ale_table();	// Added by Atsushi
            System_flush();
        }
    
    
    
    #ifndef __LINUX_USER_SPACE
        System_printf ("CSL_CPSW_getStats before Packet Transmission ...\n");
        memset(stats, 0, sizeof(stats));
        cpsw_getStats(stats, 0);
        System_flush();
    #endif
        
        /* Run some data through and verify transfer worked */
        System_printf ("Packet Transmission Start ... \n");
    #ifndef __LINUX_USER_SPACE
        for (dest_emac_port_id = 0; dest_emac_port_id < (gNum_Mac_Ports);  dest_emac_port_id ++)
        {
    #endif
    
    #ifdef SOC_C6678
        /* Only the EMAC port 1 is available at C667x EVM */
        if(dest_emac_port_id != (pa_EMAC_PORT_1 -1))
            continue;
    #endif
    
    	    for (i = 0; i < MAX_NUM_PACKETS; i ++)
    	    {
    #ifdef __LINUX_USER_SPACE
    	    	if (SendPacket () != 0)
    #else
    	    	if (SendPacket (dest_emac_port_id) != 0)
    #endif
    	        {
    	            System_printf ("Packet %d send failed \n", i);
    	            System_flush();
    	            APP_exit (-1);
    	        }
    	    }
    	    
    	    if (no_bootMode == TRUE)
    	    {
    	        System_printf("Following is the ALE table after transmits.\n");
    	        view_ale_table();
    	        System_flush();
    	    }
    	    
    	    /* Wait until all packet reception is done */
    #ifdef __LINUX_USER_SPACE
    	    System_printf ("Packet Transmission Done.\nWait for all packets to be Received ... \n");
    	    System_flush();
    #else
    	    System_printf ("Packet Transmission Done.\nWait for all packets to be Received from EMAC port %d... \n", dest_emac_port_id);
    	    System_flush();
    #endif
    	    i = 0;
    	    while ((gRxCounter != gTxCounter) && (i < MAX_RETRIES)) {
    #ifdef __LINUX_USER_SPACE
    	        if(ReceivePacket() == -1)
    	        {
    	            System_printf("Verififcation Failed for Received %d packets so far...\n", gRxCounter);
    	        }
    #endif		
    	        CycleDelay (10000);
    	        
    	        if (!cpswSimTest)
    	        {
    	    	    if (++ ct_show_ale >= 10) {
    	    		    view_ale_table();
    	    		    ct_show_ale = 0;
    	    	    }
    	        }
    	        i++;
    	    	System_printf("Received %d packets so far...\n", gRxCounter);
    	        System_flush();
    	    }
    	    
    	    System_printf ("Packets Sent\t\t=\t%d \nPackets Received\t=\t%d\n", gTxCounter,  gRxCounter);
    	    System_flush();
            if(gRxCounter != gTxCounter)fPass = 0;
    	    gTxCounter = gRxCounter = 0;
    #ifndef __LINUX_USER_SPACE
        }
    #endif
        System_printf (" \nExample Done! \nPA Stats After Packet Transmission BEGIN ********* ... \n");
        if (getPaStats ())  {
            System_printf ("Function getPaStats failed\n");
            System_flush();
        }
    
    #ifndef __LINUX_USER_SPACE
        System_printf ("CSL_CPSW_getStats after Packet Transmission ...\n");
        cpsw_getStats(stats, 1);
    #endif
        if(fPass)
            System_printf("All tests have passed!\n");
        System_printf ("**************************************************\n");
        System_printf ("******** Ethernet Single Core Example End ********\n");
        System_printf ("**************************************************\n");
        System_flush();
    
        /* Clear framework */
    	if (clearFramework() < 0) 
    	{
            System_printf ("Failed to Clean the example application \n");
            System_flush();
    	}
    
    #if (RM) && !defined(__LINUX_USER_SPACE)
        {
            int32_t rmResult;
    
            if ((rmResult = Rm_resourceStatus(rmHandle, FALSE)) != 0)
            {
                System_printf ("Error : Number of unfreed resources : %d\n", rmResult);
                System_flush();
            }
            else
            {
                System_printf ("All resources freed successfully\n");
                System_flush();
            }
        }
    #endif
    
    #ifdef PSC_TEST
       extern Pa_Handle                               gPAInstHnd;
       Pa_resetControl (gPAInstHnd, pa_STATE_RESET);
       mainPSC();
    #endif
    
        /* Example application done. Return success */
        APP_exit (0);
    
    #ifdef __LINUX_USER_SPACE
        return 0;
    #endif    
    }
    
    /* Nothing past this point */
    
    
     

     

    #include <stdio.h>
    
    //*****************************************************
    // Power definitions
    #define PSC_BASE            0x02350000
    #define PSC_PTCMD           *( unsigned int* )( PSC_BASE+0x120 )
    #define PSC_PTSTAT          *( unsigned int* )( PSC_BASE+0x128 )
    #define PSC_PDCTL_BASE      ( PSC_BASE+0x300 )
    #define PSC_MDSTAT_BASE     ( PSC_BASE+0x800 )
    #define PSC_MDCTL_BASE      ( PSC_BASE+0xA00 )
    
    /* Modules on power domain 0 */
    #define LPSC_EMIF16_SPI  3
    #define LPSC_TSIP        4
    
    /* Modules on power domain 1 */
    #define LPSC_DEBUG       5
    #define LPSC_TETB_TRC    6
    
    /* Modules on power domain 2 */
    #define LPSC_PA          7
    #define LPSC_SGMII       8
    #define LPSC_SA          9
    
    /* Modules on power domain 3 */
    #define LPSC_PCIE        10
    
    /* Modules on power domain 4 */
    #define LPSC_SRIO        11
    
    /* Modules on power domain 5 */
    #define LPSC_HYPER       12
    
    /* Modules on power domain 6 */
    #define LPSC_RESERV      13
    
    /* Modules on power domain 7 */
    #define LPSC_MSMCRAM     14
    
    /* Modules on power domain 8 */
    #define LPSC_C0_TIM0     15
    
    /* Modules on power domain 9 */
    #define LPSC_C1_TIM1     16
    
    /* Modules on power domain 10 */
    #define LPSC_C2_TIM2     17
    
    /* Modules on power domain 11 */
    #define LPSC_C3_TIM3     18
    
    /* Modules on power domain 12 */
    #define LPSC_C4_TIM4     19
    
    /* Modules on power domain 13 */
    #define LPSC_C5_TIM5     20
    
    /* Modules on power domain 14 */
    #define LPSC_C6_TIM6     21
    
    /* Modules on power domain 15 */
    #define LPSC_C7_TIM7     22
    
    // Power domains definitions
    #define PD0         (0)     // Power Domain-0
    #define PD1         (1)     // Power Domain-1
    #define PD2         (2)     // Power Domain-2
    #define PD3         (3)     // Power Domain-3
    #define PD4         (4)     // Power Domain-4
    #define PD5         (5)     // Power Domain-5
    #define PD6         (6)     // Power Domain-6
    #define PD7         (7)     // Power Domain-7
    #define PD8         (8)     // Power Domain-8
    #define PD9         (9)     // Power Domain-9
    #define PD10        (10)    // Power Domain-10
    #define PD11        (11)    // Power Domain-11
    #define PD12        (12)    // Power Domain-12
    #define PD13        (13)    // Power Domain-13
    #define PD14        (14)    // Power Domain-14
    #define PD15        (15)    // Power Domain-15
    #define PD16        (16)    // Power Domain-16
    #define PD17        (17)    // Power Domain-17
    
    #define PSC_SWRSTDISABLE             0x0
    #define PSC_ENABLE                   0x3
    
    extern cregister unsigned int DNUM;
    
    /****************************************************************************/
    Wait_Soft( int nloop )
    {
       int i;
    
       // 1 sec ~ 40000 loop on P4 3.4GHz
       for( i = 0 ; i < nloop ; i++ )
       {
       }
    }
    
    Set_PSC_State(unsigned int pd,unsigned int id,unsigned int state)
    {
        unsigned int* mdctl;
        unsigned int* mdstat;
        unsigned int* pdctl;
        int ret=0;
    
        // printf( "Set_PSC_State for pd = %d \n",pd);
    
    
        // Only core0 can set PSC
        if (DNUM == 0)
        {
            mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * id ));
            mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * id ));
            pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * pd ));
    
            // If state is already set, do nothing
            if ( ( *mdstat & 0x1f ) == state )
            {
                return(0);
            }
    
            Wait_Soft(150);
            // Check if we got timeout error while waiting
            if (PSC_PTSTAT & (0x1 << pd))
            {
                printf( "Set_PSC_State... Timeout Error #01 pd=%d, md=%d!\n",pd, id);
                ret=1;
            }
            else
            {
                // Set power domain control
                *pdctl = (*pdctl) | 0x00000001;
    
                // Set MDCTL NEXT to new state
                *mdctl = ((*mdctl) & ~(0x1f)) | state;
    
                // Start power transition by setting PTCMD GO to 1
                PSC_PTCMD = (PSC_PTCMD) | (0x1<<pd);
    
                // Wait for PTSTAT GOSTAT to clear
                Wait_Soft(150);
                if ((PSC_PTSTAT & (0x1 << pd)) != 0 ) {
                    printf( "Set_PSC_State... Timeout Error #02 pd=%d, md=%d!\n",pd, id);
                    return 1;
                }
    
                // Verify state changed
                Wait_Soft(150);
                if(( *mdstat & 0x1f ) != state ) {
                    if ((pd == 2) && (id == 9) ) {
                        printf( "Security Accelerator disabled!\n");
                    } else {
                        printf( "Set_PSC_State... Timeout Error #03 pd=%d, md=%d!\n",pd, id);
                    }
                    return 1;
                }
            }
        }
        else
        {
            printf("DSP core #%d cannot set PSC.\n",DNUM);
        }
    
        //   printf( "Exit Set_PSC_State \n");
    
        return(ret);
    }
    
    void mainPSC(void) {
    
        Set_PSC_State(PD2, LPSC_SA, PSC_SWRSTDISABLE);
        Set_PSC_State(PD2, LPSC_SGMII, PSC_SWRSTDISABLE);
        Set_PSC_State(PD2, LPSC_PA, PSC_SWRSTDISABLE);
    
    
        Wait_Soft(100000000);
        //Then power on:
    
        Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE);
        Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE);
        Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE);
    
    }
    
    
    
    
    
    
    
    
    
    

  • Hi Eric,

    the inclusion of the PA_resetControl seems to make the soft reset work.

    So I can now burn an ethernet client program into flash

    which from hard reset or power reset opens a socket on the host

    and from which the child runtime task is read and loaded.

    I do the PA_resetControl and a shutdown( socket, 1) call before jumping to the child task.

    The child task can now reopen the socket (with same IP/Port) and do the rest of the work.

    That seems to do what I need;

    thanks a lot for your valuable assistance,

    Jack