• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 96 subscribers
  • Views 417 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H14: In DDR3 non-cacheable write accesses from DSP are made through write buffer ?

Francois P
Expert 1050 points

Part Number: 66AK2H14

Hi everyone!

I have strange result in some test, I was wondering if I have a good understanding of DDR3 cacheability.

My question is:

In DDR3 non-cacheable  write accesses from DSP are made through write buffer ?

Regards,

François

  • 0
    TI__Guru* 95265 points

    Hi,

    Not sure if this issue related to a previous post https://e2e.ti.com/support/processors/f/791/t/812259, which I still try to find an answer. If not, what do you mean "made through write buffer"?

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Hi,

    If you meant the L1D write buffer, then in the C66x corepac document: igure 1-1 C66x CorePac Block Diagram, the DDR3A is connected to MSMC ----- XMC----L2 -----L1D. 
    3.3.1 L1D Cache Architecture

    The DSP can also write data to L1D. When the DSP performs a store, the L1D performs
    the same tag comparison as it does for reads. If a valid matching tag is found, then the
    write is a “hit”, and the data is written directly into the L1D cache location. Otherwise,
    the write is a “miss” and the data is queued in the L1D write buffer.

    So even DDR is not cache-able, the DSP write still made through L1D write buffer.

    Regards, Eric 

  • 0 in reply to lding
    Expert 1050 points

    Hi Eric,

    Yes, it is related to this post.

    I mean, if L1D cache is not used, does write access transit through write buffer ?

    Regards

  • 0 in reply to lding
    Expert 1050 points

    I think your last post answer to my question. I try to understand in the related post you've mentionned above, why I could have difference between cacheable and non cacheable DDR memory when no data are stored in L1D cache.

    In both ways (cacheable and non cacheable) the write accesses must transit through the Write buffer. That I can't understand, is why with the same assembly code, I have different results between cacheable and non cacheable.

    I redive my head in this subject, and I need to be sure that write accesses transit through write buffer.

    Best Regards,

    François