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TDA4: EVM SOM design questions

John H. Gardner
Guru 56631 points

Other Parts Discussed in Thread: TDA4VM

My customer had the the following questions upon their review of our TDA4 SOM:

o   Oscillator capacitor values appear out of specification for oscillator Y1 (22.5792MHz) based on design. (TDA4x_SR1.0_DM.pdf pg 172 indicates a range of 12-24pF for each load capacitor.  However, the TI design shows 30pF components. Is there a reason for this?

o   LPDDR4 vs 4x?  What was the decision? Reason is customer is thinking about depop parts not installed in design.

o   Why was power domain for RGMII 3.3V?

o   Was there a signal integrity simulation run on the layout?  Is there any information here for review?

o   Is there any other SOM design collateral available – design implementation notes, supply calcs or simulation (WEBENCH), etc on CDDS or elsewhere?

o   What is current concept for thermal design to protect the TDA4VM and SOM?

  • 0
    TI__Guru 54675 points

    Regarding Oscillator load capacitance - the DM recommendation should be followed.  EVM crystals have not been characterized, and likely will be adjusted.

    Regarding LPDDR4 vs 4x - LPDDR4 is recommended at this time.  4x validation and characterization is being pushed out, so all customers are being pushed to LPDDR4

    All LVCMOS banks can be either 1.8V or 3.3V, and this includes RGMII interfaces.  Customers can chose either based on their design requirements.

    I'm not clear on signal integrity simulation question.  Please clarify what information you are requesting.

    All available collateral is posted on CDDS.  We do not have an Webench or similar.

    The SOM is the only expected thermal concern.  Currently EVMs are shipping with a heat sink install on the SOC.

  • 0 in reply to Robert Eschler
    TI__Guru 56631 points

    Thanks Robert - been relayed.  I'll keep you posted on the signal integrity simulation question.

  • 0 in reply to Robert Eschler
    Prodigy 40 points

    Regarding the signal integrity, I was asking from a design perspective.  Had there been a Signal Integrity analysis performed on the layout with any tool such as Orcad-SI, Mentor HyperLinx SI, etc.  It would be important information to have on hand to help evaluate if the design and the test region of the coupon would offer similar results to imply related performance.

    Thanks.

  • 0 in reply to Steven Balick80
    TI__Guru 54675 points

    There was signal integrity analysis performed, with special attention on the LPDDR4 and SERDES (USB3, PCIe, QSGMII, and DisplayPort) interfaces.  However - we don't have any summary report available to show the results of those simulations, and no report available to show how the simulations compare with measured results.  There is an LPDDR4 PCB guideline available (on CDDS), which contain information on recommended simulations for the LPDDR4 interface.  There is also an existing app note on High Speed Interface Layouts (available on TI.com), which cover PCB guidelines for USB3, PCIe, etc.  I believe an update is in-work to include DispalyPort.

    Thanks.

  • 0 in reply to Robert Eschler
    TI__Mastermind 42515 points

    John, Steven,

    do you have any further questions on this topic? Can we close the thread?

    Regards,

    Yordan

  • 0 in reply to Yordan Kamenov
    TI__Guru 56631 points

    No other questions at this time.  We'll open a new ticket if needed.  Thanks Yordan and Robert.

    John