AM6546: R5F and PRU shared memory

Any memory that is visible to PRU and R5F can be used as a shared memory between the two cores but it might be recommended to use MSMC or OCMC memory as shared memory for R5F and PRU given that is onchip memory which will provide lower latency when sharing data. Having said that let me provide pointers that are relevant to ensuring both R5F and ICSSG have access to external memory:

For ICSS access to DDR memory, refer to discussion here that indicates that PRU access to DDR requires a OCP configuration. Also note the behavior of CCS memory browser when looking at DDR memory from PRU cores:

https://e2e.ti.com/support/processors/f/791/t/784798?tisearch=e2e-sitesearch&keymatch=AM6548#pi320966filter=all&pi320966scroll=false

Please also read this note for using DDR from R5F after boot needs MPU settings to be setup:

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#run-applications-from-ddr-on-r5-cores

Regards,

Rahul