AM5728: McSPI4 MOSI issue

Patrick Oetken

Part Number: AM5728
Other Parts Discussed in Thread: BEAGLEBOARD-X15

Hello,

we are trying to use the BeagleBoard-X15's McSPI4 with the Linux spidev driver (TI SDK 5.03), but we get some confusing signals on the MOSI line. SCLK and CE lines are working as expected.

Following is the Pinmux setup for McSPI4 generated with the pearl script:

{MMC3_DAT4, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat4.spi4_sclk */
{MMC3_DAT5, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat5.spi4_d1 */
{MMC3_DAT6, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat6.spi4_d0 */
{MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat7.spi4_cs0 */

The device tree node for McSPI/spidev:

&mcspi4 {
	pinctrl-names = "default";
	status = "okay";
	spidev@0{
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <48000000>;
		reg = <0x0>;
		ti,pindir-d0-out-d1-in;
		#ti,pindir-d0-in-d1-out;
		status = "okay";
	};
};

And the output on MOSI line using linux/tools/spi/spidev_test.c:

It seems like there are two signals on this pin? We are measuring directly on the expansion connectors using a Hirose FX18-60S-0.8SV15.

We also checked IO_SET4 with the same behaviour.

Another problem is, that there are no changes on the pins if we try to switch the SPI D0 and D1 pins for input and output using the out commented line in the device tree SPI node above.

Any hints on solving these problems?

Kind Regards,

Patrick

over 6 years ago

0 Pavel Botev over 6 years ago

TI__Guru**** 170625 points

Hi Matrick,

I assume you are using AM572x McSPI4 in master mode, as this is the mode McSPI driver only support:

Patrick Oetken said:
{MMC3_DAT5, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat5.spi4_d1 */

Patrick Oetken said:
ti,pindir-d0-out-d1-in;

From what I understand you need spi4_d0 (MOSI) pin to be output and spi4_d1 (MISO) pin to be input, is that correct?

If yes, please try to resolve with updating pinmux of spi4_d1 to be input, as now it is output.

Please also provide me below values:

CTRL_CORE_PAD_MMC3_DAT5/0x4A003798

CTRL_CORE_PAD_MMC3_DAT6/0x4A00379C

McSPI4.MCSPI_MODULCTRL/0x480BA128

McSPI4.MCSPI_CH0CONF/0x480BA12C

McSPI4.MCSPI_CH0CTRL/0x480BA134

McSPI4.MCSPI_TX0/0x480BA138

McSPI4.MCSPI_DAFTX/0x480BA180

Regards,
Pavel

0 Patrick Oetken over 6 years ago in reply to Pavel Botev

Prodigy 190 points

Hello Pavel,

yes, I'm using McSPI4 in master mode.

I edited the line in mux_data.h to{MMC3_DAT5, (M1 | PIN_INPUT_PULLUP)}, now the MOSI signal looks much better.

But it seems like there are still some problems driving the pin.

In the first picture you see a very long rise time to high state between two spi write operations.

The MOSI pin is pulled high after sending 8 bits, but it never reaches high state.

Spidev settings are:

spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)

The register values using devmem2:

0x4A003798 (0xb6f82798): 0x00060001

0x4A00379C (0xb6f8879c): 0x00020001

For the other registers devmem2 returns Bus error (core dumped).

Kind regards,

Patrick Oetken

0 Pavel Botev over 6 years ago in reply to Patrick Oetken

TI__Guru**** 170625 points

Patrick Oetken said:
For the other registers devmem2 returns Bus error (core dumped).

Seems that McSPI4 module is not properly enabled. Can you check below register value with devmem2 and report the result?

CM_L4PER_MCSPI4_CLKCTRL/0x4A009808

Regards,
Pavel

0 Patrick Oetken over 6 years ago in reply to Pavel Botev

Prodigy 190 points

This is the result:



root@am57xx-evm:~# devmem2 0x4A009808 w
/dev/mem opened.
Memory mapped at address 0xb6f22000.
Read at address  0x4A009808 (0xb6f22808): 0x00030000

Edit: while running SPI commands:

root@am57xx-evm:~# devmem2 0x4A009808 w
/dev/mem opened.
Memory mapped at address 0xb6f83000.
Read at address  0x4A009808 (0xb6f83808): 0x00010002

And after the completion of the command:

root@am57xx-evm:~# devmem2 0x4A009808 w
/dev/mem opened.
Memory mapped at address 0xb6f9c000.
Read at address  0x4A009808 (0xb6f9c808): 0x00020002

Kind Regards

Patrick Oetken

0 Pavel Botev over 6 years ago in reply to Patrick Oetken

TI__Guru**** 170625 points

Patrick,

From what I understand, you still have issue with mcspi4_d0 (MOSI) output pin.

I see you have enabled internal pullup on that pin. Do you have external pullup connected on that pin? As this pin is an output, please try without any pull resistors (up/down, internal/external) and report back the result.

I also see your mcspi4_sclk pin is configured as output only. But we have a requirement for this pin to be in/out, so please update. Check AM572x TRM, section 24.4.2.1 Basic McSPI Pins for Master Mode

Please also provide me McSPI4 module registers "while running SPI commands" and "after the completion of the command".

Regards,
Pavel

0 Patrick Oetken over 6 years ago in reply to Pavel Botev

Prodigy 190 points

Yes, the mcspi4_d0 signal looks not as it should.

I just tried the MOSI/D0 without pullup with the same issue described above.

How can I get the u-boot pinmux to configure mcspi4_sclk as in/out? Do I need to add two lines? For example:

{MMC3_DAT4, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat4.spi4_sclk */

{MMC3_DAT4, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat4.spi4_sclk */

I think the second line will override the register value of the first one.

For me, the description in 24.4.2.1 Basic McSPI Pins for Master Mode doesn't describe that the SCLK pin needs to be in/out. Figure 24-73 shows SPICLK as an output and also table 24-288 describes the pin as an output.

While sending:

 CTRL_CORE_PAD_MMC3_DAT5:
/dev/mem opened.
Memory mapped at address 0xb6fc6000.
Read at address  0x4A003798 (0xb6fc6798): 0x00060001
CTRL_CORE_PAD_MMC3_DAT6:
/dev/mem opened.
Memory mapped at address 0xb6f07000.
Read at address  0x4A00379C (0xb6f0779c): 0x00010001
McSPI4.MCSPI_MODULCTRL:
/dev/mem opened.
Memory mapped at address 0xb6f67000.
Read at address  0x480BA128 (0xb6f67128): 0x00000001
McSPI4.MCSPI_CH0CONF:
/dev/mem opened.
Memory mapped at address 0xb6fe2000.
Read at address  0x480BA12C (0xb6fe212c): 0x200103C0
McSPI4.MCSPI_CH0CTRL:
/dev/mem opened.
Memory mapped at address 0xb6f4f000.
Read at address  0x480BA134 (0xb6f4f134): 0x00000000
McSPI4.MCSPI_TX0:
/dev/mem opened.
Memory mapped at address 0xb6f7a000.
Read at address  0x480BA138 (0xb6f7a138): 0x00000000
McSPI4.MCSPI_DAFTX:
/dev/mem opened.
Memory mapped at address 0xb6f9f000.
Read at address  0x480BA180 (0xb6f9f180): 0x00000000
CM_L4PER_MCSPI4_CLKCTRL:
/dev/mem opened.
Memory mapped at address 0xb6fe0000.
Read at address  0x4A009808 (0xb6fe0808): 0x00000002

(Directly) after sending:

 CTRL_CORE_PAD_MMC3_DAT5:
/dev/mem opened.
Memory mapped at address 0xb6f5b000.
Read at address  0x4A003798 (0xb6f5b798): 0x00060001
CTRL_CORE_PAD_MMC3_DAT6:
/dev/mem opened.
Memory mapped at address 0xb6f22000.
Read at address  0x4A00379C (0xb6f2279c): 0x00010001
McSPI4.MCSPI_MODULCTRL:
/dev/mem opened.
Memory mapped at address 0xb6fa4000.
Read at address  0x480BA128 (0xb6fa4128): 0x00000001
McSPI4.MCSPI_CH0CONF:
/dev/mem opened.
Memory mapped at address 0xb6f9b000.
Read at address  0x480BA12C (0xb6f9b12c): 0x200103C0
McSPI4.MCSPI_CH0CTRL:
/dev/mem opened.
Memory mapped at address 0xb6f23000.
Read at address  0x480BA134 (0xb6f23134): 0x00000000
McSPI4.MCSPI_TX0:
/dev/mem opened.
Memory mapped at address 0xb6fb0000.
Read at address  0x480BA138 (0xb6fb0138): 0x00000000
McSPI4.MCSPI_DAFTX:
/dev/mem opened.
Memory mapped at address 0xb6f08000.
Read at address  0x480BA180 (0xb6f08180): 0x00000000
CM_L4PER_MCSPI4_CLKCTRL:
/dev/mem opened.
Memory mapped at address 0xb6f08000.
Read at address  0x4A009808 (0xb6f08808): 0x00020002

Kind Regards,

Patrick Oetken

0 Pavel Botev over 6 years ago in reply to Patrick Oetken

TI__Guru**** 170625 points

Patrick Oetken said:

How can I get the u-boot pinmux to configure mcspi4_sclk as in/out? Do I need to add two lines? For example:

{MMC3_DAT4, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat4.spi4_sclk */

{MMC3_DAT4, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat4.spi4_sclk */

I think the second line will override the register value of the first one.

You need below line only:

{MMC3_DAT4, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat4.spi4_sclk */

Patrick Oetken said:
For me, the description in 24.4.2.1 Basic McSPI Pins for Master Mode doesn't describe that the SCLK pin needs to be in/out. Figure 24-73 shows SPICLK as an output and also table 24-288 describes the pin as an output.

NOTE: For the spim_sclk signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.

Patrick Oetken said:

McSPI4.MCSPI_CH0CONF:

/dev/mem opened.

Memory mapped at address 0xb6fe2000.

Read at address 0x480BA12C (0xb6fe212c): 0x200103C0

This does not look correct.

[16] DPE0 = 1

[17] DPE1 = 0

[18] IS = 0

This configuration is for mcspi4_d0 input and mcspi4_d1 output.

Please modify your DTS file like below and try again.

&mcspi4 { 
    - pinctrl-names = "default"; 
    status = "okay"; 
       + ti,pindir-d0-out-d1-in;
    spidev@0{ 
        compatible = "rohm,dh2228fv"; 
        spi-max-frequency = <48000000>; 
        reg = <0x0>; 
         - ti,pindir-d0-out-d1-in; 
         - #ti,pindir-d0-in-d1-out; 
         - status = "okay"; 
    }; 
};

0 Patrick Oetken over 6 years ago in reply to Pavel Botev

Prodigy 190 points

The device tree modification solved it. The signal looks much better and the SPI slave is already working. Thank you very much!

It would be interesting to use a Cortex-M4 IPU with McSPI4 to offload the A15 cores. I found the MCSPI_Loopback_idkAM572x_m4ExampleProject in PDK, but it uses the AM572x IDK and McSPI1 instead of McSPI4. If I'm right, I need to port it to evmAM572x and after that I only need to switch MCSPI_INSTANCE from 0 to 3 and all needed registers should be set by u-boot or the McSPI library?

Kind Regards,

Patrick Oetken

0 Pavel Botev over 6 years ago in reply to Patrick Oetken

TI__Guru**** 170625 points

Patrick,

Patrick Oetken said:
The device tree modification solved it. The signal looks much better and the SPI slave is already working. Thank you very much!

As you are fine now with Linux McSPI4 MOSI issue, please close/verify/resolve this thread.

Then open new e2e thread regarding RTOS Cortex-M4 IPU McSPI4 issue.

Regards,
Pavel

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AM5728: McSPI4 MOSI issue