Part Number: TMS320C6678
Tool/software: Code Composer Studio
There are 10 ddr chips. Five chips is on the front of the board and connected to CS0, anthor five chips is on the back of the board and connected to CS1. There are one chip for ecc in every five chips.
The data width of each ddr chip is 16 bits .
There are no problems when the ddr frequency is below 1000MHz, also include 1000MHz. But the problem in picture below is arised when the frequency is 1600MHz. The picture below was got from high-speed oscilloscope.
My question: how to adjust the phase of clock to meet timing requirement.
