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TMS320C6678: Safe power down sequencing

James Sanchez
Intellectual 315 points

Part Number: TMS320C6678

Complying with the SPRS691 C6678 DSP Core-Before-IO power sequencing requirements, we successfully boot and operate our C6678 DSP, but I have a question regarding power down.

In terms of equipment safety, I am curious if there is a recommended power down sequence in the case where a C6678 power rail falls outside of regulation limits.

 

Question 1:

In such a case I would think the power down sequence would be the exact reverse of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1.  Is this correct?

 

Question 2:

Secondly, in the event a C6678 power rail falls outside of regulation limits, should the resets (RESET_N, POR_N, RESETFULL_N) also be asserted in the reverse order of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1, or should they be asserted simultaneously?

 

I use an FPGA to control the power up / power down sequencing of the C6678 and want to make sure that my power down sequencing gives the DSP the best chance to survive such an event.

 

Thank you very much for your time,

Jim Sanchez

  • 0
    TI__Guru**** 161600 points

    Hi Jim,

    Question 1: Yes, your understanding is correct. Power-down sequence is the exact reverse of the power-up sequence.

    Question 2: The datasheet states:
        If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

    Hope this helps.

    Best Regards,
    Yordan