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AM3356: I2C DMA cache issue

techGeek
Prodigy 70 points

Part Number: AM3356

I am using DMA for i2c communication

During read and write i am facing data corruption issues.

I have enabled MMU.

I have observed during my debugging that at certain times the data corruption happens.

I have used the following API's during read/write

1) After i2c DMA read used CleanInvalidateDcache();

2) Before i2c DMA write CleanDcache();

When i disable MMU, i am not facing the data corruption issue. 

Please let me know is there any issue while using DMA with MMU enabled.

Thanks for the help in advance

  • 0
    TI__Guru**** 393215 points

    Please post which SDK and what version you are using.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 70 points

    Hi Biser,

    Thanks for the quick reply.

    We are using PDK_AM335x_1_0_13 without RTOS.

    Regards,

    Manjunath

  • 0 in reply to techGeek
    TI__Guru** 116960 points

    What is the MMU settings for the memory region in question.  HEre is the recommended MMU setting while using I2C peripheral from one of our RTOS setups where this is working without any issues.

    /* ================ Cache and MMU configuration ================ */

var Cache = xdc.useModule('ti.sysbios.family.arm.a8.Cache');
Cache.enableCache = true;

var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
Mmu.enableMMU = true;

/* Force peripheral section to be NON cacheable strongly-ordered memory */
var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 0,
bufferable : false, // bufferable
cacheable : false, // cacheable
shareable : false, // shareable
noexecute : true, // not executable
};

/* Define the base address of the 1 Meg page the peripheral resides in. */
var peripheralBaseAddr = 0x44e00400;;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);


/* Define the base address of the 1 Meg page the peripheral resides in. */
var peripheralBaseAddr = 0x481a6000;

/* Configure the corresponding MMU page descriptor accordingly */
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

    Hope this helps.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 70 points

    Hi Rahul,

    Thanks for the input.

    I'll check configurations and will revert back.

    Regards,

    Manjunath

  • 0 in reply to Rahul Prabhu
    Prodigy 70 points

    Hi Rahul,

    I have missed out the following part hinted by you:

    /* Force peripheral section to be NON cacheable strongly-ordered memory */
    var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    tex: 0,
    bufferable : false, // bufferable
    cacheable : false, // cacheable
    shareable : false, // shareable
    noexecute : true, // not executable
    };

    It worked, Thanks for the help:)

    Regards,

    Manjunath