Part Number: TDA2SG
Dear Champs,
Per below post, a patch is applied to kernel to support early boot late attach. The patch is to disable EDMA setup in kernel since EDMA has been setup in M4.
https://e2e.ti.com/support/processors/f/791/t/826484
From c11eef98b07a8c9093f2f5c71f8ba40451559e86 Mon Sep 17 00:00:00 2001
From: Shravan Karthik <shravan.karthik@ti.com>
Date: Mon, 31 Jul 2017 10:24:20 +0530
Subject: [PATCH 2/4] arm: mach-omap2: Remove edma related nodes from hwmod
init sequence
When doing late attach, kernel should not reset EDMA
EDMA is setup by M4 and thus omap_hwmod needn't perform reset/setup.
Nodes 'dra7xx_l3_main_1__tpcc', 'dra7xx_l3_main_1__tptc0' and
'dra7xx_l3_main_1__tptc1' are thus disabled.
Note that this breaks kernel boot if not late attached.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 26fcb1e..ff11cb2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -4637,9 +4637,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per2__mcasp8,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
- &dra7xx_l3_main_1__tpcc,
- &dra7xx_l3_main_1__tptc0,
- &dra7xx_l3_main_1__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_dsp1__l3_main_1,
--
2.7.4
But I still see below edma failures from linux boot log
[ 0.451929] platform 43300000.edma: Cannot lookup hwmod 'tpcc'
[ 0.458283] platform 43400000.tptc: Cannot lookup hwmod 'tptc0'
[ 0.464732] platform 43500000.tptc: Cannot lookup hwmod 'tptc1'
[ 0.471968] OMAP GPIO hardware version 0.1
[ 0.482582] irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 !
[ 0.510660] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[ 0.518967] hw-breakpoint: maximum watchpoint size is 8 bytes.
[ 0.525501] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[ 0.533184] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[ 0.541138] OMAP DMA hardware revision 0.0
[ 0.621211] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[ 0.631491] edma3-tptc 43400000.tptc: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info
[ 0.640733] edma3-tptc 43500000.tptc: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info
[ 0.650170] edma 43300000.edma: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info
[ 0.658837] edma 43300000.edma: pm_runtime_get_sync() failed
[ 0.668458] omap-iommu 40d01000.mmu: 40d01000.mmu registered
I think the failures comes for device tree because the default device tree still try to setup EDMA
http://git.ti.com/glsdk/infoadas-kernel/blobs/HEAD/arch/arm/boot/dts/dra7.dtsi
edma: edma@43300000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x43300000 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
};
edma_tptc0: tptc@43400000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x43400000 0x100000>;
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@43500000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x43500000 0x100000>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
My questions:
1. Sould I modify the device tree by removing the EDMA setup? Or I can just leave it unchanged and ignore the EDMA failures?
2. Per below post, TI has provided a EDMA kernel space driver. When using early boot late attach, EDMA is setup in M4 not A15. I would like to know if this driver can still work in such case.
https://e2e.ti.com/support/processors/f/791/t/826808
Thanks.
