320x240 PRGB for DM355

You may be able to get 6.75 MHz ( 27 / 4 ) VCLK using DLCKPTN registers; however, I do not believe this would affect CDOUT_HSYNC; in order to accomplish both, you may need to resort to an exetrnal clock source via PCLK pin.

Juan,

I am not very professional developer, I just have 6 months experience, normally what is the best solution for that implementation?

How can we use that PRGB TFT?  I saw that with some bootargs commands , we can arrange screen size and type (NTSC, PAL and LCD), Is it a good way?

thank you

This is a question of what hardware / software you have available.  For example, our DM355 EVM has a 27 MHz and composite analog video output; this is only good for NTSC/PAL analog video output.  You can display a cropped 320x240 video window inside the NTSC/PAL frame, but that is about it.

If you have additional hardware (e.g. LCD daughter card, THS8200 daughtercard), then you can use some more software driver features; in particular these daughter cards can be used to have digital video output such as progressive RGB (PGRB) which it appears is what you want.  Therefore, if you configure DM355 for digital PRGB video output, I assume you have the corresponding daughter card to be able to see this video output.  Please note that in th eTHS8200 case, the daughter card provides a 74.25 MHZ external clock into DM355 allowing it to support 720p and 1080i video standards (both which require 74.25 MHz per insdustry standards).

Therefore, to answer your questions, yes bootargs commands is a good way to start, but you need to ensure you have the proper hardware; otherwise these options will not due much for you.

Dear Juan,

We have prepared on our connection card PCB for our TFT. There is a SAMTECH's connector also that PCB. We connected TFT to EVM via this card with DC5. We connected CDOUT_HSYNC to HSYNC, CDOUT_VSYNC to VSYNC and RGB pins. But as far as I see that, HSYNC and VSYNC frequencies are not compatible with the TFT's so I did some changes on Kernel to get this resolution and frequency.

Firstly I changed at "dm355fb.c" the function as

set_dm_default_conf()

{

.......................................

     dm->display.mode = LCD;

     dm->display.interface =PRGB;

..................................................

}

the secondly I changed the definition of DISP_XRES and DISP_YRES as 320 and 240, then I make some changes on

struct vpbe_videomode_prgb[ ] = {

    {"PRGB_480",FB_MODE_NOINTERLACED,320,240,60,89,70,34,11,9,9,0,0x59,0x22,1},

.....................................................................................................................

.....................................................................................................................

}

I make this kind of changes on Kernel, and also I have to say that, the physical connection is very  PRGB from EVM to TFT, what is your suggestion for that situation?

I try to explain my situation , but If there is a nonclear point please tell me.

I achieved to get 6.75MHz DCLK now.

dispc_reg_out(VENC_DCLKCTL, 0x0A01); 

but I could'nt arange the VSYNC and HSYNC. How Can I change them? 

canibeksağın,have you solved your problem?since i have the much same question.