AM4377: Ethernet RMII send fails

phy link err=0x7849,id=0x2000,5c90;

[ver2019.0328appM]��pltMain start!

[ver2019.0328appM]:pltMain start!


cpu2 hw init;

AM437X_FlashInit 0 open...
AM437X_UartInit 0 open...
uart0 baud set...
uart0 Set baud = 115200
AM437X_UartInit 4 open...
creat task t_uart4R;

dma ER=14000a00,0,EER=28000500,0;

ccReg:0;0;0;0;0;0;0;

tcReg:0;0;0;0;0;0;0;

RParam:chl=4,opt=0x8010a000,src=0x481a8000,dst=0x82e8a000,Acnt=1,Bcnt=10240,Ccnt1;
srcBid=0,dstBid=1,srcCid=0,dstCid=1,link=0x4480,BcntRld=0;
uart4 baud set...
uart4 Set baud = 3000000
set sio4 baud 3000000;

AM437X_UartInit 1 open...
creat task t_uart1R;

dma ER=14000a00,0,EER=28000500,0;

ccReg:0;0;0;0;0;0;0;

tcReg:0;0;0;0;0;0;0;

RParam:chl=1,opt=0x8011d000,src=0x48022000,dst=0x82e8d000,Acnt=1,Bcnt=10240,Ccnt1;
srcBid=0,dstBid=1,srcCid=0,dstCid=1,link=0x4420,BcntRld=0;
uart1 baud set...
uart1 Set baud = 3000000
set sio1 baud 3000000;

AM437X_UartInit 3 open...
creat task t_uart3R;

dma ER=14000a00,0,EER=28000500,0;

ccReg:0;0;0;0;0;0;0;

tcReg:0;0;0;0;0;0;0;

RParam:chl=3,opt=0x80108000,src=0x481a6000,dst=0x82e90000,Acnt=1,Bcnt=10240,Ccnt1;
srcBid=0,dstBid=1,srcCid=0,dstCid=1,link=0x4460,BcntRld=0;
uart3 baud set...
uart3 Set baud = 3000000
set sio3 baud 3000000;

AM437X_TemprInit 0 open...
AM437X_AdcInit open...
gpio test:

gpio0 open...
gpio1 open...
gpio2 open...
gpio3 open...
gpio4 open...
gpio5 open...
gpio6 open...
gpio7 open...
gpio9 open...
failed to open /dev/gpiofd/85(9,0x55,0)=0xffffffff!
gpio10 open...
gpio11 open...
gpio12 open...
failed to open /dev/gpiofd/138(12,0x8a,0)=0xffffffff!
gpio13 open...
gpio14 open...
gpio15 open...


AM437X_AdcSelfTest:

adc0 rev msg size=140:

[0x0]= 0 10001 20002 30003 40004 50005 60006 70007

[0x20]= 0 0 0 0 0 0 0 0

[0x40]= d4e(1.497V) 10d51(1.498V) 209ca(1.101V) 309cb(1.101V) 40000 50000 60000 70000

[0x60]= 0 0 0 0 0 0 0 0

[0x80]= 6 0 8

adc get volt test:
volt(0~3)=0x5de(1.502V) 0x5da(1.498V) 0x44d(1.101V) 0x44f(1.103V) 

adc get tempr test:
tempr=0x2e00(46.0��C);

the offset is 0xe0000
erase1
0xe0000 BER64,0xf0000 SER,0xf1000 SER,0xf2000 SER,0xf3000 SER,0xf4000 SER,0xf5000 SER,
erase2
0xf5000 SER,0xf6000 SER,0xf7000 SER,0xf8000 SER,0xf9000 SER,0xfa000 SER,0xfb000 SER,0xfc000 SER,0xfd000 SER,0xfe000 SER,0xff000 SER,0x100000 SER,read1

read2 0xf4f80

write1 0xf4f80
read1 0xf4f80

write2
read2

test os flash:addr0xe0200,len13312;
write and read:
ers addr0xe0000(e3000),size0x4000;left=512,2560;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 00 00 00 00 00 00 00 00 00 00 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 54 00 00 01 02 2d b1 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 55 00 00 01 02 2d b0 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 ea 03 00 00 00 01 04 00 00 00 ef ff ff fa 00 00 00 00 00 00;

mac0 r L96: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 26 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 ff 5e 14 eb 00 26;

mac0 r L76: 01 00 5e 00 00 fc 00 04 23 a7 22 f4 08 00 45 00 00 3a 55 56 00 00 01 11 c1 ac c0 a8 01 0c e0 00 00 fc c0 27 14 eb 00 26 1b b4 1d 9a 00 00 00 01 00 00 00 00 00 00 0c 78 38 30 31 30;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 57 00 00 01 11 b2 46 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 58 00 00 01 11 b2 45 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L66: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 30 55 59 00 00 01 02 2d a4 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 05 06 00 00 00 02 04 00 00 00 e0 00 00 fc 04 00 00 00 ef ff;

mac0 r L114: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 38 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 00 00 00 00 00 00 00 00 00 00 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

0xe0000 SER,0xe1000 SER,0xe2000 SER,0xe3000 SER,0xe4000 SER,
erase and read:
mac0 r L90: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 20 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 f2 e1 14 eb 00 20;

mac0 r L70: 01 00 5e 00 00 fc 00 04 23 a7 22 f4 08 00 45 00 00 34 55 5a 00 00 01 11 c1 ae c0 a8 01 0c e0 00 00 fc f3 9c 14 eb 00 20 3c ba b9 8b 00 00 00 01 00 00 00 00 00 00 06 69 73 61 74 61;

0xe0000 SER,0xe1000 SER,0xe2000 SER,0xe3000 SER,0xe4000 SER,flash0 ers 0xe0000 size=16384:
clkRate=1000;tick0=12601;pltPktBufInit ok,blkChlNum=53/83(12+12+10/40+9+10)start0x8063de04!

can not open dir /var/log0=2 No such file or directory!
c0logAdd0

log file0 size init1=0B;

log file0 size init2=0B;

can not open dir /var/log1=2 No such file or directory!
c1logAdd0

log file1 size init1=0B;

log file1 size init2=0B;

can not open dir /var/log2=2 No such file or directory!
c2logAdd0

log file2 size init1=0B;

log file2 size init2=0B;

can not open dir /var/log3=2 No such file or directory!
c3logAdd0

log file3 size init1=0B;

log file3 size init2=0B;

pltMain pltSysLog ok!

[c2]logW:T000031e8-APP0-0P1-0:

[c2]logW:pltMain PL

PHY 1 Performing Auto-Negotiation...
[c2]logW:T_SendMsgT

CPSW0 port1 phy dump:


[c2]logW:oLog ok!



phy reg0~7= 1000(0) 786d(1) 2000(2) 5c90(3) 1e1(4) c1e1(5) f(6) 2801(7);

[c2]logW:

phy reg0x10~0x1D= 4015(10) 1(11) 2c00(12) 0(13) 0(14) 0(15) 100(16) 21(17) 0(18) 8021(19) 904(1a) 0(1b) 0(1c) 6011(1d);

rmii pinmux cfg:TXEN=3,TXD1=3,TXD0=3,RXD1=40003,

RXD0=40003,CRS_DV=60003,RXER=40003,REFCLK=40001,MDIO_DATA=20000,MDIO_CLK=60000,;

phy ctl=1000;

PHY 1 Auto-Negotiation Successful(c200).
CPSW0 port1 phy dump:


phy reg0~7= 1000(0) 786d(1) 2000(2) 5c90(3) 1e1(4) c1e1(5) d(6) 2801(7);

phy reg0x10~0x1D= 4615(10) 1(11) 0(12) 0(13) 0(14) 0(15) 100(16) 21(17) 0(18) 8021(19) 904(1a) 0(1b) 0(1c) 6011(1d);

rmii pinmux cfg:TXEN=3,TXD1=3,TXD0=3,RXD1=40003,

RXD0=40003,CRS_DV=60003,RXER=40003,REFCLK=40001,MDIO_DATA=20000,MDIO_CLK=60000,;

PHY 1 Transfer Mode : 100 Mbps Full Duplex.
mac t L60/60: ff ff ff ff ff ff b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 01 b0 d5 cc 75 56 26 c0 a8 01 eb 00 00 00 00 00 00 c0 a8 01 eb b9 8b 00 00 00 01 00 00 00 00 00 00 06 69 73 61 74 61;

cpsw tx job done!

netif en1 link up
mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 5b 00 00 01 02 2d aa c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 fa 01 00 00 00 01 03 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 5c 00 00 01 02 2d a9 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 5e 00 00 40 11 a0 d3 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea e0 ed c4 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 5f 00 00 40 11 a0 d2 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 d8 ed c5 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 60 00 00 40 11 a0 d1 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea dc ed c6 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L96: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 26 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 fc 76 14 eb 00 26;

mac0 r L76: 01 00 5e 00 00 fc 00 04 23 a7 22 f4 08 00 45 00 00 3a 55 61 00 00 01 11 c1 a1 c0 a8 01 0c e0 00 00 fc c1 58 14 eb 00 26 93 e5 a4 37 00 00 00 01 00 00 00 00 00 00 0c 78 38 30 31 30;

mac t L86/86: 33 33 ff 75 56 26 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 20 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 00 00 00 01 ff 75 56 26 3a 00 05 02 00 00;

mac t L78/78: 33 33 ff 75 56 26 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 18 3a ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 00 00 00 01 ff 75 56 26 87 00 51 1a 00 00;

cpsw tx job done!

mac t L62/62: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 08 3a ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 7b b8 00 00;

cpsw tx job done!

cpsw tx job done!

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L86/86: 33 33 ff 75 56 26 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 20 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 00 00 00 01 ff 75 56 26 3a 00 05 02 00 00;

cpsw tx job done!

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 63 00 00 01 02 2d a2 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 64 00 00 40 11 a0 cd c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea dc ed c6 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 65 00 00 40 11 a0 cc c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 d8 ed c5 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 66 00 00 40 11 a0 cb c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea e0 ed c4 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 67 00 00 01 11 b2 36 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L74: 33 33 00 00 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 47 9a 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 68 00 00 01 11 b2 35 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 69 00 00 01 11 b2 34 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 6a 00 00 40 11 a0 c7 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea e0 ed c4 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 6b 00 00 40 11 a0 c6 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 d8 ed c5 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 6c 00 00 40 11 a0 c5 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea dc ed c6 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac t L86/86: 33 33 ff 75 56 26 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 20 00 01 fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 01 ff 75 56 26 3a 00 05 02 00 00;

cpsw tx job done!

mac0 r L90: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 20 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 e3 4e 14 eb 00 20;

mac0 r L70: 01 00 5e 00 00 fc 00 04 23 a7 22 f4 08 00 45 00 00 34 55 6d 00 00 01 11 c1 9b c0 a8 01 0c e0 00 00 fc d9 38 14 eb 00 20 e5 af 2a fa 00 00 00 01 00 00 00 00 00 00 06 69 73 61 74 61;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 6e 00 00 40 11 a0 d5 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 d1 ed c7 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 6f 00 00 40 11 a0 c2 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c eb dc ed c6 28 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 70 00 00 40 11 a0 c1 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 59 d8 ed c5 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 71 00 00 40 11 a0 c0 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c eb e0 ed c4 28 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

patrol zone <KERNEL-DATA> complete.
mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 72 00 00 40 11 a0 d1 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 d1 ed c7 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 74 00 00 40 11 a0 bd c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a d2 ed ca 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 76 00 00 40 11 a0 cd c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 d1 ed c7 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 77 00 00 40 11 a0 ba c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a d2 ed ca 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 78 00 00 01 11 b2 25 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L70/70: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 d4 4a 00 00;

cpsw tx job done!

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 79 00 00 40 11 a0 ca c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 cd ed cb 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 7a 00 00 40 11 a0 b7 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a d2 ed ca 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L74: 33 33 00 00 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 47 9a 00 00;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 7b 00 00 40 11 a0 c8 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 cd ed cb 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 7c 00 00 40 11 a0 b5 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4b d2 ed ca 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 7d 00 00 40 11 a0 c6 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 cd ed cb 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 7e 00 00 40 11 a0 40 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 f0 11 02 ed ce c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L247: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 e5 55 7f 00 00 40 11 a0 2d c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 d1 5d c9 11 02 ed cf c0 a8 01 0c 00 8a 00 bb 00 00 20 46 49 44;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 80 00 00 40 11 a0 c3 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 c8 ed d0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 81 00 00 01 11 b2 1c c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 82 00 00 40 11 a0 c1 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 c8 ed d0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 83 00 00 40 11 a0 3b c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 eb 11 02 ed d3 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

patrol zone <EXT-DATA> complete.
mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 84 00 00 40 11 a0 bf c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 c8 ed d0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac t L70/70: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 d4 4a 00 00;

cpsw tx job done!

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 8a 00 00 40 11 a0 34 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 ea 11 02 ed d4 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 8c 00 00 01 11 b2 11 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 8d 00 00 40 11 a0 31 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 e9 11 02 ed d5 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 eb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L60/60: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 02 b0 d5 cc 75 56 26 c0 a8 01 eb 00 04 23 a7 22 f4 c0 a8 01 0c ed c6 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

cpsw tx job done!

mac0 r L78: b0 d5 cc 75 56 26 00 04 23 a7 22 f4 08 00 45 00 00 3c 55 8e 00 00 40 01 a0 eb c0 a8 01 0c c0 a8 01 eb 08 00 39 1e 00 01 14 3d 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

mac t L74/74: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 00 45 00 00 3c 55 8e 00 00 ff 01 e1 ea c0 a8 01 eb c0 a8 01 0c 00 00 41 1e 00 01 14 3d 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

cpsw tx job done!

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 8f 00 00 40 11 a0 23 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb c9 c9 11 02 ed d6 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L78: b0 d5 cc 75 56 26 00 04 23 a7 22 f4 08 00 45 00 00 3c 55 90 00 00 40 01 a0 e9 c0 a8 01 0c c0 a8 01 eb 08 00 39 1d 00 01 14 3e 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

mac t L74/74: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 00 45 00 00 3c 55 90 00 00 ff 01 e1 e8 c0 a8 01 eb c0 a8 01 0c 00 00 41 1d 00 01 14 3e 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

cpsw tx job done!

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 91 00 00 01 11 b2 0c c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 92 00 00 40 11 a0 20 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb c9 c8 11 02 ed d7 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L78: b0 d5 cc 75 56 26 00 04 23 a7 22 f4 08 00 45 00 00 3c 55 93 00 00 40 01 a0 e6 c0 a8 01 0c c0 a8 01 eb 08 00 39 1c 00 01 14 3f 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

mac t L74/74: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 00 45 00 00 3c 55 93 00 00 ff 01 e1 e5 c0 a8 01 eb c0 a8 01 0c 00 00 41 1c 00 01 14 3f 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

cpsw tx job done!

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 94 00 00 40 11 a0 1e c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb c9 c7 11 02 ed d8 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L78: b0 d5 cc 75 56 26 00 04 23 a7 22 f4 08 00 45 00 00 3c 55 95 00 00 40 01 a0 e4 c0 a8 01 0c c0 a8 01 eb 08 00 39 1b 00 01 14 40 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

mac t L74/74: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 00 45 00 00 3c 55 95 00 00 ff 01 e1 e3 c0 a8 01 eb c0 a8 01 0c 00 00 41 1b 00 01 14 40 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72;

cpsw tx job done!

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 96 00 00 40 11 a0 1c c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb c9 c6 11 02 ed d9 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 97 00 00 01 11 b2 06 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 98 00 00 40 11 a0 99 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb c2 ed da 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 99 00 00 40 11 a0 98 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb c2 ed da 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 9a 00 00 40 11 a0 97 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb c2 ed da 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

wdg enable 0s!

wdg write start!

patrol zone <KERNEL-DATA> complete.
mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 9b 00 00 40 11 a0 96 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cc c2 ed da 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 9c 00 00 01 11 b2 01 c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 9d 00 00 40 11 a0 94 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 bf ed db 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 9e 00 00 40 11 a0 93 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 bf ed db 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 9f 00 00 40 11 a0 92 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 bf ed db 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 a0 00 00 40 11 a0 91 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 25 bf ed db 28 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 a1 00 00 01 11 b1 fc c0 a8 01 0c ef ff ff fa c0 2b 07 6c 00 8d df a3 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 a2 00 00 40 11 a0 1c c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 63 e3 11 02 ed dc c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 a3 00 00 40 11 a0 1b c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 2f df 11 02 ed dd c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L259: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 f1 55 a4 00 00 40 11 9f fc c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 dd 32 5b 11 02 ed de c0 a8 01 0c 00 8a 00 c7 00 00 20 46 49 44;

patrol zone <EXT-DATA> complete.
mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

[root@sylixos:/root]# phy link err=0x7849,id=0x2000,5c90;

netif en1 link down
phy link err=0x7849,id=0x2000,5c90;

patrol zone <EXT-DATA> complete.
phy link err=0x7849,id=0x2000,5c90;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 00 00 00 00 00 00 00 00 00 00 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L82: 33 33 ff 98 91 99 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 18 3a ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 00 00 00 01 ff 98 91 99 87 00 fc 00 00 00;

mac0 r L74: 33 33 00 00 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 47 9a 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

PHY 1 Performing Auto-Negotiation...
CPSW0 port1 phy dump:


phy reg0~7= 1000(0) 786d(1) 2000(2) 5c90(3) 1e1(4) c1e1(5) f(6) 2801(7);

phy reg0x10~0x1D= 4815(10) 1(11) 2c00(12) 0(13) 12(14) 0(15) 100(16) 21(17) 0(18) 8021(19) 904(1a) 0(1b) 0(1c) 6011(1d);

rmii pinmux cfg:TXEN=3,TXD1=3,TXD0=3,RXD1=40003,

RXD0=40003,CRS_DV=60003,RXER=40003,REFCLK=40001,MDIO_DATA=20000,MDIO_CLK=60000,;

phy ctl=1000;

PHY 1 Auto-Negotiation Successful(c200).
CPSW0 port1 phy dump:


phy reg0~7= 1000(0) 786d(1) 2000(2) 5c90(3) 1e1(4) c1e1(5) d(6) 2801(7);

phy reg0x10~0x1D= 4615(10) 1(11) 0(12) 0(13) 0(14) 0(15) 100(16) 21(17) 0(18) 8021(19) 904(1a) 0(1b) 0(1c) 6011(1d);

rmii pinmux cfg:TXEN=3,TXD1=3,TXD0=3,RXD1=40003,

RXD0=40003,CRS_DV=60003,RXER=40003,REFCLK=40001,MDIO_DATA=20000,MDIO_CLK=60000,;

PHY 1 Transfer Mode : 100 Mbps Full Duplex.
mac t L60/60: ff ff ff ff ff ff b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 01 b0 d5 cc 75 56 26 c0 a8 01 eb 00 00 00 00 00 00 c0 a8 01 eb 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

cpsw tx job done!

netif en1 link up
mac t L70/70: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 d4 4a 00 00;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac t L86/86: 33 33 ff 75 56 26 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 20 00 01 fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 01 ff 75 56 26 3a 00 05 02 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 00 00 00 00 00 00 00 00 00 00 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 ad 00 00 01 02 2d 58 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 ae 00 00 01 02 2d 57 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 ea 03 00 00 00 01 04 00 00 00 ef ff ff fa 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L66: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 30 55 af 00 00 01 02 2d 4e c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 05 06 00 00 00 02 04 00 00 00 e0 00 00 fc 04 00 00 00 ef ff;

mac0 r L114: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 38 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 00 00 00 00 00 00 00 00 00 00 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L90: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 20 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 ff e9 14 eb 00 20;

mac0 r L70: 01 00 5e 00 00 fc 00 04 23 a7 22 f4 08 00 45 00 00 34 55 b0 00 00 01 11 c1 58 c0 a8 01 0c e0 00 00 fc ed 56 14 eb 00 20 aa 20 52 6b 00 00 00 01 00 00 00 00 00 00 06 69 73 61 74 61;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 b1 00 00 01 02 2d 54 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 fa 01 00 00 00 01 03 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 b2 00 00 01 02 2d 53 c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 b3 00 00 40 11 a0 7e c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b7 ed ed 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 b4 00 00 40 11 a0 7d c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 af ed ee 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 b5 00 00 40 11 a0 7c c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b3 ed ef 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: 01 00 5e 00 00 16 00 04 23 a7 22 f4 08 00 46 00 00 28 55 b6 00 00 01 02 2d 4f c0 a8 01 0c e0 00 00 16 94 04 00 00 22 00 f9 01 00 00 00 01 04 00 00 00 e0 00 00 fc 00 00 00 00 00 00;

mac0 r L94: 33 33 00 00 00 16 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 24 00 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 16 3a 00 05 02 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 b7 00 00 01 11 b1 e6 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 b8 00 00 40 11 a0 79 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b3 ed ef 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 b9 00 00 40 11 a0 78 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 af ed ee 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 ba 00 00 40 11 a0 77 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b7 ed ed 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L74: 33 33 00 00 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 47 9a 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 bb 00 00 40 11 a0 76 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b7 ed ed 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 bc 00 00 40 11 a0 75 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 58 af ed ee 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 bd 00 00 40 11 a0 74 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c ea b3 ed ef 29 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac t L70/70: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 d4 4a 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L90: 33 33 00 01 00 03 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 20 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 03 d0 6a 14 eb 00 20;

mac0 r L70: cc cc cc cc cc cc cc cc cc cc cc cc cc cc 45 00 00 34 55 be 00 00 01 11 c1 4a c0 a8 01 0c e0 00 00 fc eb 9a 14 eb 00 20 0a fb f3 4c 00 00 00 01 00 00 00 00 00 00 06 69 73 61 74 61;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 c3 00 00 40 11 a0 6e c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c eb b7 ed ed 28 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 c4 00 00 40 11 a0 6d c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 59 af ed ee 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 c5 00 00 40 11 a0 6c c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c eb b3 ed ef 28 10 00 01 00 00 00 00 00 01 20 46 49 44 49 44;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 c6 00 00 40 11 a0 7d c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a8 ed f0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 c7 00 00 40 11 a0 6a c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a a9 ed f3 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 c8 00 00 40 11 a0 7b c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a8 ed f0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 ca 00 00 01 11 b1 d3 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 cb 00 00 01 11 b1 d2 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 cc 00 00 01 11 b1 d1 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 cd 00 00 40 11 a0 64 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a a9 ed f3 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 ce 00 00 40 11 a0 75 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a8 ed f0 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 cf 00 00 40 11 a0 62 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4a a9 ed f3 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 d0 00 00 40 11 a0 73 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a4 ed f4 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 d1 00 00 01 11 b1 cc c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L74: 33 33 00 00 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 47 9a 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 d2 00 00 40 11 a0 5f c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 4b a9 ed f3 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 d3 00 00 40 11 a0 70 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a4 ed f4 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L70/70: 33 33 00 00 00 02 b0 d5 cc 75 56 26 86 dd 60 00 00 00 00 10 3a ff fe 80 00 00 00 00 00 00 b2 d5 cc ff fe 75 56 26 patrol zone <KERNEL-DATA> complete.
ff 02 00 00 00 00 00 00 00 00 00 00 00 00 00 02 85 00 d4 4a 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 d4 00 00 40 11 9f ea c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 c7 11 02 ed f7 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L247: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 e5 55 d5 00 00 40 11 9f d7 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 d1 5d a0 11 02 ed f8 c0 a8 01 0c 00 8a 00 bb 00 00 20 46 49 44;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 d6 00 00 40 11 a0 6d c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 a4 ed f4 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 d7 00 00 01 11 b1 c6 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 d8 00 00 01 11 b1 c5 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 d9 00 00 40 11 a0 6a c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 9f ed f9 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 da 00 00 40 11 9f e4 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 c2 11 02 ed fc c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 db 00 00 40 11 a0 68 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 9f ed f9 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 dc 00 00 01 11 b1 c1 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L96: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 4e 55 dd 00 00 40 11 a0 66 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 3a 44 9f ed f9 01 10 00 01 00 00 00 00 00 00 20 45 4a 46 44 45;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 de 00 00 40 11 9f e0 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 c1 11 02 ed fd c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 df 00 00 40 11 9f df c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 56 c0 11 02 ed fe c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 e0 00 00 01 11 b1 bd c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

patrol zone <EXT-DATA> complete.
mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L158: 33 33 00 01 00 02 00 04 23 a7 22 f4 86 dd 60 00 00 00 00 64 11 01 fe 80 00 00 00 00 00 00 74 8c ea 35 fd 98 91 99 ff 02 00 00 00 00 00 00 00 00 00 00 00 01 00 02 02 22 02 23 00 64;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 e1 00 00 40 11 9f d1 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb e1 54 11 02 ed ff c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 e2 00 00 40 11 9f d0 c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb e1 53 11 02 ee 00 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 e3 00 00 01 11 b1 ba c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 e4 00 00 40 11 9f ce c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb e1 52 11 02 ee 01 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L241: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 df 55 e5 00 00 40 11 9f cd c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 cb e1 51 11 02 ee 02 c0 a8 01 0c 00 8a 00 b5 00 00 20 46 49 44;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 e6 00 00 40 11 a0 4b c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb 99 ee 03 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 e7 00 00 01 11 b1 b6 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 e8 00 00 40 11 a0 49 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb 99 ee 03 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 eb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L60/60: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 02 b0 d5 cc 75 56 26 c0 a8 01 eb 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 ea 00 00 40 11 a0 47 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cb 99 ee 03 29 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 eb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L60/60: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 02 b0 d5 cc 75 56 26 c0 a8 01 eb 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 eb 00 00 40 11 a0 46 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c cc 99 ee 03 28 10 00 01 00 00 00 00 00 01 20 46 48 45 50 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 eb 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac t L60/60: 00 04 23 a7 22 f4 b0 d5 cc 75 56 26 08 06 00 01 08 00 06 04 00 02 b0 d5 cc 75 56 26 c0 a8 01 eb 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 ec 00 00 40 11 a0 45 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 96 ee 04 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L179: 01 00 5e 7f ff fa 00 04 23 a7 22 f4 08 00 45 00 00 a1 55 ed 00 00 01 11 b1 b0 c0 a8 01 0c ef ff ff fa ef cc 07 6c 00 8d b0 02 4d 2d 53 45 41 52 43 48 20 2a 20 48 54 54 50 2f 31 2e;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 ee 00 00 40 11 a0 43 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 96 ee 04 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L64: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 06 00 01 08 00 06 04 00 01 00 04 23 a7 22 f4 c0 a8 01 0c 00 00 00 00 00 00 c0 a8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;

mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 f0 00 00 40 11 a0 41 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 24 96 ee 04 29 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

patrol zone <KERNEL-DATA> complete.
mac0 r L114: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 60 55 f1 00 00 40 11 a0 40 c0 a8 01 0c c0 a8 01 ff 00 89 00 89 00 4c 25 96 ee 04 28 10 00 01 00 00 00 00 00 01 20 41 42 41 43 46;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 f2 00 00 40 11 9f cc c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 63 ba 11 02 ee 05 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L229: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 d3 55 f3 00 00 40 11 9f cb c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 bf 2f b6 11 02 ee 06 c0 a8 01 0c 00 8a 00 a9 00 00 20 46 49 44;

mac0 r L259: ff ff ff ff ff ff 00 04 23 a7 22 f4 08 00 45 00 00 f1 55 f4 00 00 40 11 9f ac c0 a8 01 0c c0 a8 01 ff 00 8a 00 8a 00 dd 32 32 11 02 ee 07 c0 a8 01 0c 00 8a 00 c7 00 00 20 46 49 44;

/*
 * Board functions for CRSCD AM437X based board
 *
 * Copyright (C) 2018 crscd Ltd - http://www.crscd.com/
 *
 * Author: xiaoyiping <xiaoyiping@crscd.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/errno.h>
#include <spl.h>
#include <usb.h>
#include <asm/omap_sec_common.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mux.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "../common/board_detect.h"
#include "board.h"
#include <power/pmic.h>
#include <power/tps65218.h>
#include <power/tps62362.h>
#include <miiphy.h>
#include <cpsw.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>

DECLARE_GLOBAL_DATA_PTR;

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /*cpu��version��Ϣ��ַ*/

/*add@20180308 for crsc ͬ��myir spl���߱��ļ���ע��spl��ش���*/
#if 0
/*
 * Read header information from EEPROM into global structure.
 */
#ifdef CONFIG_TI_I2C_BOARD_DETECT
void do_board_detect(void)
{
	if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
		printf("ti_i2c_eeprom_init failed\n");
}
#endif

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

#define NUM_OPPS	6

const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
	{	/* 19.2 MHz */
		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
	},
	{	/* 24 MHz */
		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
	},
	{	/* 25 MHz */
		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
	},
	{	/* 26 MHz */
		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
	},
};

const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
};

const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
};

const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
		{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
		{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
};

const struct dpll_params gp_evm_dpll_ddr = {
		50, 2, 1, -1, 2, -1, -1};

static const struct dpll_params idk_dpll_ddr = {
	400, 23, 1, -1, 2, -1, -1
};

static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
	0x00500050,
	0x00350035,
	0x00350035,
	0x00350035,
	0x00350035,
	0x00350035,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x40001000,
	0x08102040
};

const struct ctrl_ioregs ioregs_lpddr2 = {
	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
	.emif_sdram_config_ext	= 0x1,
};

const struct emif_regs emif_regs_lpddr2 = {
	.sdram_config			= 0x808012BA,
	.ref_ctrl			= 0x0000040D,
	.sdram_tim1			= 0xEA86B411,
	.sdram_tim2			= 0x103A094A,
	.sdram_tim3			= 0x0F6BA37F,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074BE4,
	.temp_alert_config		= 0x0,
	.emif_rd_wr_lvl_rmp_win		= 0x0,
	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
	.emif_rd_wr_lvl_ctl		= 0x0,
	.emif_ddr_phy_ctlr_1		= 0x0E284006,
	.emif_rd_wr_exec_thresh		= 0x80000405,
	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
	.emif_prio_class_serv_map	= 0x80000001,
	.emif_connect_id_serv_1_map	= 0x80000094,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config			= 0x000FFFFF
};

const struct ctrl_ioregs ioregs_ddr3 = {
	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
	.emif_sdram_config_ext	= 0xc163,
};

const struct emif_regs ddr3_emif_regs_400Mhz = {
	.sdram_config			= 0x638413B2,
	.ref_ctrl			= 0x00000C30,
	.sdram_tim1			= 0xEAAAD4DB,
	.sdram_tim2			= 0x266B7FDA,
	.sdram_tim3			= 0x107F8678,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074BE4,
	.temp_alert_config		= 0x0,
	.emif_ddr_phy_ctlr_1		= 0x0E004008,
	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
	.emif_rd_wr_lvl_rmp_win		= 0x0,
	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
	.emif_rd_wr_lvl_ctl		= 0x0,
	.emif_rd_wr_exec_thresh		= 0x80000405,
	.emif_prio_class_serv_map	= 0x80000001,
	.emif_connect_id_serv_1_map	= 0x80000094,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config		= 0x000FFFFF
};

/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
	.sdram_config			= 0x638413B2,
	.ref_ctrl			= 0x00000C30,
	.sdram_tim1			= 0xEAAAD4DB,
	.sdram_tim2			= 0x266B7FDA,
	.sdram_tim3			= 0x107F8678,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074BE4,
	.temp_alert_config		= 0x0,
	.emif_ddr_phy_ctlr_1		= 0x0E004008,
	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
	.emif_rd_wr_exec_thresh		= 0x80000405,
	.emif_prio_class_serv_map	= 0x80000001,
	.emif_connect_id_serv_1_map	= 0x80000094,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config		= 0x000FFFFF
};

/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
const struct emif_regs ddr3_emif_regs_400Mhz_production = {
	.sdram_config			= 0x638413B2,
	.ref_ctrl			= 0x00000C30,
	.sdram_tim1			= 0xEAAAD4DB,
	.sdram_tim2			= 0x266B7FDA,
	.sdram_tim3			= 0x107F8678,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074BE4,
	.temp_alert_config		= 0x0,
	.emif_ddr_phy_ctlr_1		= 0x0E004008,
	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
	.emif_rd_wr_exec_thresh		= 0x80000405,
	.emif_prio_class_serv_map	= 0x80000001,
	.emif_connect_id_serv_1_map	= 0x80000094,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config		= 0x000FFFFF
};

static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
	.sdram_config			= 0x638413b2,
	.sdram_config2			= 0x00000000,
	.ref_ctrl			= 0x00000c30,
	.sdram_tim1			= 0xeaaad4db,
	.sdram_tim2			= 0x266b7fda,
	.sdram_tim3			= 0x107f8678,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074be4,
	.temp_alert_config		= 0x0,
	.emif_ddr_phy_ctlr_1		= 0x0e084008,
	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x89,
	.emif_ddr_ext_phy_ctrl_3	= 0x90,
	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
	.emif_rd_wr_lvl_rmp_win		= 0x0,
	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
	.emif_rd_wr_lvl_ctl		= 0x00000000,
	.emif_rd_wr_exec_thresh		= 0x80000000,
	.emif_prio_class_serv_map	= 0x80000001,
	.emif_connect_id_serv_1_map	= 0x80000094,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config		= 0x000FFFFF
};

static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
	.sdram_config			= 0x61a11b32,
	.sdram_config2			= 0x00000000,
	.ref_ctrl			= 0x00000c30,
	.sdram_tim1			= 0xeaaad4db,
	.sdram_tim2			= 0x266b7fda,
	.sdram_tim3			= 0x107f8678,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x50074be4,
	.temp_alert_config		= 0x00000000,
	.emif_ddr_phy_ctlr_1		= 0x00008009,
	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
	.emif_rd_wr_lvl_ctl		= 0x00000000,
	.emif_rd_wr_exec_thresh		= 0x00000405,
	.emif_prio_class_serv_map	= 0x00000000,
	.emif_connect_id_serv_1_map	= 0x00000000,
	.emif_connect_id_serv_2_map	= 0x00000000,
	.emif_cos_config		= 0x00ffffff
};

void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
	if (board_is_eposevm()) {
		*regs = ext_phy_ctrl_const_base_lpddr2;
		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
	}

	return;
}

/*
 * get_sys_clk_index : returns the index of the sys_clk read from
 *			ctrl status register. This value is either
 *			read from efuse or sysboot pins.
 */
static u32 get_sys_clk_index(void)
{
	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
	u32 ind = readl(&ctrl->statusreg), src;

	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
	else /* Value read from SYS BOOT pins */
		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
			CTRL_SYSBOOT_15_14_SHIFT);
}

const struct dpll_params *get_dpll_ddr_params(void)
{
	int ind = get_sys_clk_index();

	if (board_is_eposevm())
		return &epos_evm_dpll_ddr[ind];
	else if (board_is_evm() || board_is_sk())
		return &gp_evm_dpll_ddr;
	else if (board_is_idk())
		return &idk_dpll_ddr;

	printf(" Board '%s' not supported\n", board_ti_get_name());
	return NULL;
}


/*
 * get_opp_offset:
 * Returns the index for safest OPP of the device to boot.
 * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
 * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
 * This data is read from dev_attribute register which is e-fused.
 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 * OPP available. Lowest OPP starts with min_off. So returning the
 * bit with rightmost '0'.
 */
static int get_opp_offset(int max_off, int min_off)
{
	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
	int opp, offset, i;

	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;

	for (i = max_off; i >= min_off; i--) {
		offset = opp & (1 << i);
		if (!offset)
			return i;
	}

	return min_off;
}

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const struct dpll_params *get_dpll_mpu_params(void)
{
	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
	u32 ind = get_sys_clk_index();

	return &dpll_mpu[ind][opp];
}

const struct dpll_params *get_dpll_core_params(void)
{
	int ind = get_sys_clk_index();

	return &dpll_core[ind];
}

const struct dpll_params *get_dpll_per_params(void)
{
	int ind = get_sys_clk_index();

	return &dpll_per[ind];
}

void scale_vcores_generic(u32 m)
{
	int mpu_vdd;

	if (i2c_probe(TPS65218_CHIP_PM))
		return;

	switch (m) {
	case 1000:
		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
		break;
	case 800:
		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
		break;
	case 720:
		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
		break;
	case 600:
		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
		break;
	case 300:
		mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
		break;
	default:
		puts("Unknown MPU clock, not scaling\n");
		return;
	}

	/* Set DCDC1 (CORE) voltage to 1.1V */
	if (tps65218_voltage_update(TPS65218_DCDC1,
				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
		printf("%s failure\n", __func__);
		return;
	}

	/* Set DCDC2 (MPU) voltage */
	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
		printf("%s failure\n", __func__);
		return;
	}
}

void scale_vcores_idk(u32 m)
{
	int mpu_vdd;

	if (i2c_probe(TPS62362_I2C_ADDR))
		return;

	switch (m) {
	case 1000:
		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
		break;
	case 800:
		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
		break;
	case 720:
		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
		break;
	case 600:
		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
		break;
	case 300:
		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
		break;
	default:
		puts("Unknown MPU clock, not scaling\n");
		return;
	}

	/* Set VDD_MPU voltage */
	if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
		printf("%s failure\n", __func__);
		return;
	}
}

void gpi2c_init(void)
{
	/* When needed to be invoked prior to BSS initialization */
	static bool first_time = true;

	if (first_time) {
		enable_i2c0_pin_mux();
		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
			 CONFIG_SYS_OMAP24_I2C_SLAVE);
		first_time = false;
	}
}

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void scale_vcores(void)
{
	const struct dpll_params *mpu_params;

	/* Ensure I2C is initialized for PMIC configuration */
	gpi2c_init();

	/* Get the frequency */
	mpu_params = get_dpll_mpu_params();

	if (board_is_idk())
		scale_vcores_idk(mpu_params->m);
	else
		scale_vcores_generic(mpu_params->m);
}

#endif
#endif

/*���ļ�����xxx�б��� ������Ҫ�Ƶ�mux.c��*/
/*��2���ӿڷ�װ���armv7/am33xx���ṩ�ӿڡ�*/
#if 0
void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_board_pin_mux();
}
#endif

#if 0
#if 0
static void enable_vtt_regulator(void)
{
	u32 temp;

	/* enable module */
	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);

	/* enable output for GPIO5_7 */
	writel(GPIO_SETDATAOUT(7),
	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
	temp = temp & ~(GPIO_OE_ENABLE(7));
	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
}

enum {
	RTC_BOARD_EPOS = 1,
	RTC_BOARD_EVM14,
	RTC_BOARD_EVM12,
	RTC_BOARD_GPEVM,
	RTC_BOARD_SK,
};

/*
 * In the rtc_only boot path we have the board type info in the rtc scratch pad
 * register hence we bypass the costly i2c reads to eeprom and directly program
 * the board name string
 */
void rtc_only_update_board_type(u32 btype)
{
	const char *name = "";
	const char *rev = "1.0";

	switch (btype) {
	case RTC_BOARD_EPOS:
		name = "AM43EPOS";
		break;
	case RTC_BOARD_EVM14:
		name = "AM43__GP";
		rev = "1.4";
		break;
	case RTC_BOARD_EVM12:
		name = "AM43__GP";
		rev = "1.2";
		break;
	case RTC_BOARD_GPEVM:
		name = "AM43__GP";
		break;
	case RTC_BOARD_SK:
		name = "AM43__SK";
		break;
	}
	ti_i2c_eeprom_am_set(name, rev);
}

u32 rtc_only_get_board_type(void)
{
	if (board_is_eposevm())
		return RTC_BOARD_EPOS;
	else if (board_is_evm_14_or_later())
		return RTC_BOARD_EVM14;
	else if (board_is_evm_12_or_later())
		return RTC_BOARD_EVM12;
	else if (board_is_gpevm())
		return RTC_BOARD_GPEVM;
	else if (board_is_sk())
		return RTC_BOARD_SK;

	return 0;
}

void sdram_init(void)
{
	/*
	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
	 * GP EMV has 1GB DDR3 connected to EMIF
	 * along with VTT regulator.
	 */
	if (board_is_eposevm()) {
		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
	} else if (board_is_evm_14_or_later()) {
		enable_vtt_regulator();
		config_ddr(0, &ioregs_ddr3, NULL, NULL,
			   &ddr3_emif_regs_400Mhz_production, 0);
	} else if (board_is_evm_12_or_later()) {
		enable_vtt_regulator();
		config_ddr(0, &ioregs_ddr3, NULL, NULL,
			   &ddr3_emif_regs_400Mhz_beta, 0);
	} else if (board_is_evm()) {
		enable_vtt_regulator();
		config_ddr(0, &ioregs_ddr3, NULL, NULL,
			   &ddr3_emif_regs_400Mhz, 0);
	} else if (board_is_sk()) {
		config_ddr(400, &ioregs_ddr3, NULL, NULL,
			   &ddr3_sk_emif_regs_400Mhz, 0);
	} else if (board_is_idk()) {
		config_ddr(400, &ioregs_ddr3, NULL, NULL,
			   &ddr3_idk_emif_regs_400Mhz, 0);
	}
}
#endif
#endif

/* setup board specific PMIC */
int power_init_board(void)
{
	struct pmic *p;
	uchar tps_status = 0;

    puts("PMIC:  TPS65218 skip!\n");
    return 0;

/*add@20180308 for crsc ͬ��myir ʹ��65218��ԴоƬ*/
#if 0
	if (board_is_idk()) {
		power_tps62362_init(I2C_PMIC);
		p = pmic_get("TPS62362");
		if (p && !pmic_probe(p))
			puts("PMIC:  TPS62362\n");
	} else 
#else
    if(board_is_crsc_c437x_idk())
#endif
	{
		power_tps65218_init(I2C_PMIC);
		p = pmic_get("TPS65218_PMIC");
		if (p && !pmic_probe(p))
		{
			puts("PMIC:  TPS65218\n");
			
			/*begin:add@20180308 for crsc ͬ��myir*/
			/* We don't care if fseal is locked, but we do need it set */
			tps65218_lock_fseal();
			tps65218_reg_read(TPS65218_STATUS, &tps_status);
			if (!(tps_status & TPS65218_FSEAL))
				printf("WARNING: RTC not backed by battery!\n");
		    /*end:add@20180308 for crsc ͬ��myir*/
		}
	}

	return 0;
}

int board_init(void)
{
	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
	    modena_init0_bw_integer, modena_init0_watermark_0;

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	gpmc_init();

	/* Clear all important bits for DSS errata that may need to be tweaked*/
	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
	                   MREQPRIO_0_SAB_INIT0_MASK;

	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;

	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
	                                   BW_LIMITER_BW_FRAC_MASK;

	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
	                                BW_LIMITER_BW_INT_MASK;

	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
	                                 BW_LIMITER_BW_WATERMARK_MASK;

	/* Setting MReq Priority of the DSS*/
	mreqprio_0 |= 0x77;

	/*
	 * Set L3 Fast Configuration Register
	 * Limiting bandwith for ARM core to 700 MBPS
	 */
	modena_init0_bw_fractional |= 0x10;
	modena_init0_bw_integer |= 0x3;

	writel(mreqprio_0, &cdev->mreqprio_0);
	writel(mreqprio_1, &cdev->mreqprio_1);

	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	set_board_info_env("crsc_c437x_idk");

	/*
	 * Default FIT boot on HS devices. Non FIT images are not allowed
	 * on HS devices.
	 */
	if (get_device_type() == HS_DEVICE)
		setenv("boot_fit", "1");
#endif
	return 0;
}
#endif

#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = USB_OTG_SS1_BASE,
	.tx_fifo_resize = false,
	.index = 0,
};

static struct dwc3_omap_device usb_otg_ss1_glue = {
	.base = (void *)USB_OTG_SS1_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 0,
};

static struct ti_usb_phy_device usb_phy1_device = {
	.usb2_phy_power = (void *)USB2_PHY1_POWER,
	.index = 0,
};

static struct dwc3_device usb_otg_ss2 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = USB_OTG_SS2_BASE,
	.tx_fifo_resize = false,
	.index = 1,
};

static struct dwc3_omap_device usb_otg_ss2_glue = {
	.base = (void *)USB_OTG_SS2_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.index = 1,
};

static struct ti_usb_phy_device usb_phy2_device = {
	.usb2_phy_power = (void *)USB2_PHY2_POWER,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	u32 status;

	status = dwc3_omap_uboot_interrupt_status(index);
	if (status)
		dwc3_uboot_handle_interrupt(index);

	return 0;
}
#endif /* CONFIG_USB_DWC3 */

#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
	enable_usb_clocks(index);
#ifdef CONFIG_USB_DWC3
	switch (index) {
	case 0:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
			ti_usb_phy_uboot_init(&usb_phy1_device);
			dwc3_uboot_init(&usb_otg_ss1);
		}
		break;
	case 1:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
			ti_usb_phy_uboot_init(&usb_phy2_device);
			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
			dwc3_uboot_init(&usb_otg_ss2);
		}
		break;
	default:
		printf("Invalid Controller Index\n");
	}
#endif

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
#ifdef CONFIG_USB_DWC3
	switch (index) {
	case 0:
	case 1:
		if (init == USB_INIT_DEVICE) {
			ti_usb_phy_uboot_exit(index);
			dwc3_uboot_exit(index);
			dwc3_omap_uboot_exit(index);
		}
		break;
	default:
		printf("Invalid Controller Index\n");
	}
#endif
	disable_usb_clocks(index);

	return 0;
}
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */

#ifndef CONFIG_DM_ETH  /*crsc��ǰ�����ˣ��򲻱������²���*/
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* Additional controls can be added here */
	return;
}

/*add@20180308 for crsc ͬ��myir���Ӷ����ʼֵ*/
static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208, /*CPSW_PORT 0x4A10_0100+108h: CPSW_PORT_P1_MAX_BLKS*/
		.sliver_reg_ofs	= 0xd80, /*CPSW_SL1 0x4A10_0D80: Ethernet Sliver for Port 1*/
		.phy_addr	= 0, 
	},
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 1,
	},
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 4,
	},
	{
		.slave_reg_ofs	= 0x308, /*CPSW_PORT 0x4A10_0100+208h: CPSW_PORT_P2_MAX_BLKS*/
		.sliver_reg_ofs	= 0xdc0, /*CPSW_SL2 0x4A10_0DC0: Ethernet Sliver for Port 2*/
		.phy_addr	= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs = 0xdc0,
		.phy_addr	= 1,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs = 0xdc0,
		.phy_addr	= 4,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,  /*CPSW_MDIO 0x4A10_1000*/
	.cpsw_base		= CPSW_BASE,  /*0x4A10_0000*/
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs	= 0x800,
	.slaves			= 6, /*add@20180308 for crsc ͬ��myir��1��Ϊ6��ɨ����slave��ַ*/
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		    = 0x2000,
	.mac_control		= (1 << 5),
	.control		    = cpsw_control,
	.host_port_num		= 0,
	.version		    = CPSW_CTRL_VERSION_2,
};
#endif

/*
 * This function will:
 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 * in the environment
 * Perform fixups to the PHY present on certain boards.  We only need this
 * function in:
 * - SPL with either CPSW or USB ethernet support
 * - Full U-Boot, with either CPSW or USB ethernet
 * Build in only these cases to avoid warnings about unused variables
 * when we build an SPL that has neither option but full U-Boot will.
 */
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
	defined(CONFIG_SPL_USBETH_SUPPORT)) && \
	defined(CONFIG_SPL_BUILD)) || \
	((defined(CONFIG_DRIVER_TI_CPSW) || \
	  defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
	int rv;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

    /*crsc���� cpu2��Ҫ��ʼ��
    if (board_is_crsc_c437x_idk())
    {
        puts("crsc_c437x not support eth!\n");
        return 0;
    }*/

	/* try reading mac address from efuse ��cpu�Ĵ�������macֵ*/
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

#ifndef CONFIG_SPL_BUILD
	mac_lo = readl(&cdev->macid1l);
	mac_hi = readl(&cdev->macid1h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

	if (!getenv("eth1addr")) {
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("eth1addr", mac_addr);
	}

#endif

/*add@20180308 for crsc ͬ��myir ע��������֧*/
#if 0
	if (board_is_eposevm()) {
		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
		cpsw_slaves[0].phy_addr = 16;
	} else if (board_is_sk()) {
		writel(RGMII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
		cpsw_slaves[0].phy_addr = 4;
		cpsw_slaves[1].phy_addr = 5;
	} else if (board_is_idk()) 
#else
    if (board_is_crsc_c437x_idk())
#endif
	{
		//writel(RGMII_MODE_ENABLE, &cdev->miisel);
		/*RMIIѡ������CPU�IJο�ʱ��*/
		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
        cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
        cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
        cpsw_slaves[2].phy_if = PHY_INTERFACE_MODE_RMII;
		cpsw_slaves[3].phy_if = PHY_INTERFACE_MODE_RMII;
        cpsw_slaves[4].phy_if = PHY_INTERFACE_MODE_RMII;
        cpsw_slaves[5].phy_if = PHY_INTERFACE_MODE_RMII;
		/*cpsw_slaves[0].phy_addr = 4; ��0��Ϊ4����ע����*/
	} 
#if 0
	else {
		writel(RGMII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
		cpsw_slaves[0].phy_addr = 0;
	}
#endif

	rv = cpsw_register(&cpsw_data);
	if (rv < 0) {
		printf("Error %d registering CPSW switch\n", rv);
		return rv;
	}
#endif
#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
	if (is_valid_ethaddr(mac_addr))
		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
#endif

	return rv;
}
#endif
#endif

/*add@20180308 for crsc ���ļ�����spl�б��룬��Ҫ���˺����Ƶ�spl.c��*/
#if 0
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/*add@20180308 for crsc*/
#if 0
	if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
		return 0;
	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
		return 0;
	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
		return 0;
	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
		return 0;
	else
		return -1;
#else
    if (board_is_crsc_c437x_idk() && !strcmp(name, "crsc_c437x"))
    {
        return 0;
    }
    else
    {
        return -1;
    }
#endif
}
#endif
#endif

#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
	secure_boot_verify_image(p_image, p_size);
}
#endif

CONFIG_ARM=y
CONFIG_AM43XX=y
CONFIG_CRSC_I2C_BOARD_DETECT=y
CONFIG_TARGET_CRSC_C437X=y
CONFIG_DM_SERIAL=y
# CONFIG_DM_SPI=y
# CONFIG_DM_SPI_FLASH=y
CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="crsc_c437x"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_PROMPT="CRSC># "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DMA=y
# CONFIG_DM_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
# CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
CONFIG_FIT=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_LIST="crsc_c437x"
# CONFIG_DM_ETH=y
CONFIG_DM_NAND=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_CMD_TIME=y
# CONFIG_DM_I2C=y