Other Parts Discussed in Thread: DP83867IS
Hi Everyone,
I am using custom K2HK board and PDK_06_00_00_07 for software (u-boot and kernel),
I need clarification on the device tree in LINUX for NETCP DMA ( ti,navigator-dmas = <&dma_gbe 22>, /* rx flow for CPSW port 0 */) , how to configure rx_flow value to bring up below mention phy-2 and phy-3 mapped to Gbe-2 and Gbe-3.
The K2HK EVM has two Marvell eth Phy, On our custom board we have 4 eth Phy (first two marvell 88e1111 and other two DP83867IS) all have configured for 4-wire SGMII between Phy and MAC.
At u-boot using first TI DP83867IS (Phy-2)we are able to ping (packet transmission is happing in both way, RX as well as TX),
but with second TI DP83867IS (Phy-3) ping is failing only one-way TX traffic is their (packet are coming out of K2HK board, but there is no RX packet),
At Linux using both TI DP83867IS Phy-2 and Phy3 ping is failing only one-way TX traffic is there.(DP83867 Linux driver is ported from u-boot ti.c driver)
Please find attached device tree file and NETCP node configure like below.
dma-coherent;
ti,navigator-dmas = <&dma_gbe 22>, /* rx flow for CPSW port 0 */
<&dma_gbe 23>, /* rx flow for CPSW port 1 */
<&dma_gbe 24>, /* rx flow for CPSW port 2 */
<&dma_gbe 25>, /* rx flow for CPSW port 3 */
<&dma_gbe 8>; /* CPSW tx channel */
ti,navigator-dma-names = "netrx0",
"netrx1",
"netrx2",
"netrx3",
"nettx";
While debugging at u-boot found that for both phy-2 and phy3 rx_flow is 24(as per device tree configuration rx_flow should be 24 for phy-2 and 25 for phy-3).
Any working Reference for device tree for NETCP dma rx_flow at Linux is most welcome.
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for Keystone 2 Hawking Netcp driver
*
* Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
*/
qmss: qmss@2a40000 {
compatible = "ti,keystone-navigator-qmss";
dma-coherent;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&chipclk13>;
ranges;
queue-range = <0 0x4000>;
linkram0 = <0x100000 0x8000>;
linkram1 = <0x0 0x10000>;
qmgrs {
#address-cells = <1>;
#size-cells = <1>;
ranges;
qmgr0 {
managed-queues = <0 0x2000>;
reg = <0x2a40000 0x20000>,
<0x2a06000 0x400>,
<0x2a02000 0x1000>,
<0x2a03000 0x1000>,
<0x23a80000 0x20000>,
<0x2a80000 0x20000>;
reg-names = "peek", "status", "config",
"region", "push", "pop";
};
qmgr1 {
managed-queues = <0x2000 0x2000>;
reg = <0x2a60000 0x20000>,
<0x2a06400 0x400>,
<0x2a04000 0x1000>,
<0x2a05000 0x1000>,
<0x23aa0000 0x20000>,
<0x2aa0000 0x20000>;
reg-names = "peek", "status", "config",
"region", "push", "pop";
};
};
queue-pools {
qpend {
qpend-0 {
qrange = <658 8>;
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
0 43 0xf04 0 44 0xf04 0 45 0xf04
0 46 0xf04 0 47 0xf04>;
};
qpend-1 {
qrange = <8704 16>;
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
0 51 0xf04 0 52 0xf04 0 53 0xf04
0 54 0xf04 0 55 0xf04 0 56 0xf04
0 57 0xf04 0 58 0xf04 0 59 0xf04
0 60 0xf04 0 61 0xf04 0 62 0xf04
0 63 0xf04>;
qalloc-by-id;
};
qpend-2 {
qrange = <8720 16>;
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
0 59 0xf04 0 68 0xf04 0 69 0xf04
0 70 0xf04 0 71 0xf04 0 72 0xf04
0 73 0xf04 0 74 0xf04 0 75 0xf04
0 76 0xf04 0 77 0xf04 0 78 0xf04
0 79 0xf04>;
};
};
general-purpose {
gp-0 {
qrange = <4000 64>;
};
netcp-tx {
qrange = <640 9>;
qalloc-by-id;
};
netcpx-tx {
qrange = <8752 8>;
qalloc-by-id;
};
};
accumulator {
acc-low-0 {
qrange = <480 32>;
accumulator = <0 47 16 2 50>;
interrupts = <0 226 0xf01>;
multi-queue;
qalloc-by-id;
};
};
};
descriptor-regions {
#address-cells = <1>;
#size-cells = <1>;
ranges;
region-12 {
id = <12>;
region-spec = <8192 128>; /* num_desc desc_size */
link-index = <0x4000>;
};
};
pdsps {
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdsp0@0x2a10000 {
reg = <0x2a10000 0x1000 /*iram */
0x2a0f000 0x100 /*reg*/
0x2a0c000 0x3c8 /*intd */
0x2a20000 0x4000>; /*cmd*/
id = <0>;
};
};
}; /* qmss */
knav_dmas: knav_dmas@0 {
compatible = "ti,keystone-navigator-dma";
clocks = <&papllclk>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,navigator-cloud-address = <0x23a80000 0x23a90000
0x23aa0000 0x23ab0000>;
dma_gbe: dma_gbe@0 {
reg = <0x2004000 0x100>,
<0x2004400 0x120>,
<0x2004800 0x300>,
<0x2004c00 0x120>,
<0x2005000 0x400>;
reg-names = "global", "txchan", "rxchan",
"txsched", "rxflow";
ti,enable-all;
};
};
gbe_subsys: subsys@2090000 {
compatible = "syscon";
reg = <0x02090000 0x100>;
};
gbe_serdes: phy@232a000 {
compatible = "ti,keystone-serdes-gbe";
reg = <0x0232a000 0x2000>;
status = "disabled";
link-rate-kbps = <1250000>;
num-lanes = <4>;
#address-cells = <1>;
#size-cells = <0>;
serdes_lane0: lane@0 {
#phy-cells = <0>;
reg = <0>;
status = "ok";
control-rate = <2>;
rx-start = <7 5>;
rx-force = <1 1>;
tx-coeff = <0 0 0 12 4>;
};
serdes_lane1: lane@1 {
#phy-cells = <0>;
reg = <1>;
status = "ok";
control-rate = <2>;
rx-start = <7 5>;
rx-force = <1 1>;
tx-coeff = <0 0 0 12 4>;
};
serdes_lane2: lane@2 {
#phy-cells = <0>;
reg = <2>;
status = "ok";
control-rate = <2>;
rx-start = <7 5>;
rx-force = <1 1>;
tx-coeff = <0 0 0 12 4>;
};
serdes_lane3: lane@3 {
#phy-cells = <0>;
reg = <3>;
status = "ok";
control-rate = <2>;
rx-start = <7 5>;
rx-force = <1 1>;
tx-coeff = <0 0 0 12 4>;
};
};
netcp: netcp@2000000 {
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
#address-cells = <1>;
#size-cells = <1>;
/* NetCP address range */
ranges = <0 0x2000000 0x100000>;
clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
clock-names = "pa_clk", "ethss_clk", "cpts";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 22>, /* rx flow for CPSW port 0 */
<&dma_gbe 23>, /* rx flow for CPSW port 1 */
<&dma_gbe 24>, /* rx flow for CPSW port 2 */
<&dma_gbe 25>, /* rx flow for CPSW port 3 */
<&dma_gbe 8>; /* CPSW tx channel */
ti,navigator-dma-names = "netrx0",
"netrx1",
"netrx2",
"netrx3",
"nettx";
netcp-devices {
ranges;
#address-cells = <1>;
#size-cells = <1>;
gbe@90000 { /* ETHSS */
#address-cells = <1>;
#size-cells = <1>;
label = "netcp-gbe";
compatible = "ti,netcp-gbe";
syscon-subsys = <&gbe_subsys>;
reg = <0x90100 0x200>, <0x90400 0x200>, <0x90800 0x700>;
tx-queue = <648>;
tx-channel = "nettx";
interfaces {
gbe0: interface-0 {
phys = <&serdes_lane0>;
slave-port = <0>;
link-interface = <1>;
phy-handle = <ðphy0>;
};
gbe1: interface-1 {
phys = <&serdes_lane1>;
slave-port = <1>;
link-interface = <1>;
phy-handle = <ðphy1>;
};
gbe2: interface-2 {
status = "ok";
phys = <&serdes_lane2>;
slave-port = <2>;
link-interface = <1>;
phy-handle = <ðphy2>;
};
gbe3: interface-3 {
status = "ok";
phys = <&serdes_lane3>;
slave-port = <3>;
link-interface = <1>;
phy-handle = <ðphy3>;
};
};
};
};
netcp-interfaces {
interface-0 {
rx-channel = "netrx0";
rx-pool = <1024 12>;
tx-pool = <1024 12>;
rx-queue-depth = <128 128 0 0>;
rx-buffer-size = <1518 4096 0 0>;
rx-queue = <8704>;
tx-completion-queue = <8708>;
efuse-mac = <1>;
netcp-gbe = <&gbe0>;
};
interface-1 {
rx-channel = "netrx1";
rx-pool = <1024 12>;
tx-pool = <1024 12>;
rx-queue-depth = <128 128 0 0>;
rx-buffer-size = <1518 4096 0 0>;
rx-queue = <8705>;
tx-completion-queue = <8709>;
efuse-mac = <0>;
local-mac-address = [02 18 31 7e 3e 6f];
netcp-gbe = <&gbe1>;
};
interface-2 {
status = "ok";
rx-channel = "netrx2";
rx-pool = <1024 12>;
tx-pool = <1024 12>;
rx-queue-depth = <128 128 0 0>;
rx-buffer-size = <1518 4096 0 0>;
rx-queue = <8706>;
tx-completion-queue = <8710>;
efuse-mac = <0>;
local-mac-address = [02 18 31 7e 3e 6e];
netcp-gbe = <&gbe2>;
};
interface-3 {
status = "ok";
rx-channel = "netrx3";
rx-pool = <1024 12>;
tx-pool = <1024 12>;
rx-queue-depth = <128 128 0 0>;
rx-buffer-size = <1518 4096 0 0>;
rx-queue = <8707>;
tx-completion-queue = <8711>;
efuse-mac = <0>;
local-mac-address = [02 18 31 7e 3e 6d];
netcp-gbe = <&gbe3>;
};
};
};
sa_subsys: subsys@20c0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x20c0000 0x40000>;
sa_config: subsys@0 {
compatible = "syscon";
reg = <0x0 0x100>;
};
rng@24000 {
compatible = "ti,keystone-rng";
reg = <0x24000 0x1000>;
ti,syscon-sa-cfg = <&sa_config>;
clocks = <&clksa>;
clock-names = "fck";
};
};
// SPDX-License-Identifier: GPL-2.0
/*
* Keystone 2 Kepler/Hawking EVM device tree
*
* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "keystone.dtsi"
#include "keystone-k2hk.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dsp_common_memory: dsp-common-memory@81f800000 {
compatible = "shared-dma-pool";
reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
reusable;
status = "okay";
};
dsp_common_mpm_memory: dsp-common-mpm-memory@820000000 {
compatible = "ti,keystone-dsp-mem-pool";
reg = <0x00000008 0x20000000 0x00000000 0x10000000>;
no-map;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
debug1_1 {
label = "keystone:green:debug1";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
};
debug1_2 {
label = "keystone:red:debug1";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
};
debug2 {
label = "keystone:blue:debug2";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
};
debug3 {
label = "keystone:blue:debug3";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
};
};
};
&soc0 {
clocks {
refclksys: refclksys {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <122880000>;
clock-output-names = "refclk-sys";
};
refclkpass: refclkpass {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <122880000>;
clock-output-names = "refclk-pass";
};
refclkarm: refclkarm {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "refclk-arm";
};
refclkddr3a: refclkddr3a {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "refclk-ddr3a";
};
refclkddr3b: refclkddr3b {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "refclk-ddr3b";
};
};
};
&usb_phy {
status = "okay";
};
&keystone_usb0 {
status = "okay";
};
&usb0 {
dr_mode = "host";
};
&aemif {
cs0 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <0>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <12>;
ti,cs-read-hold-ns = <6>;
ti,cs-read-strobe-ns = <23>;
ti,cs-read-setup-ns = <9>;
ti,cs-write-hold-ns = <8>;
ti,cs-write-strobe-ns = <23>;
ti,cs-write-setup-ns = <8>;
nand@0,0 {
compatible = "ti,keystone-nand","ti,davinci-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x4000000
1 0 0x0000100>;
ti,davinci-chipselect = <0>;
ti,davinci-mask-ale = <0x2000>;
ti,davinci-mask-cle = <0x4000>;
ti,davinci-mask-chipsel = <0>;
nand-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
nand-on-flash-bbt;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "params";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "ubifs";
reg = <0x180000 0x1fe80000>;
};
};
};
};
&i2c0 {
dtt@50 {
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
&spi0 {
nor_flash: n25q128a11@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "Micron,n25q128a11";
spi-max-frequency = <54000000>;
m25p,fast-read;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "misc";
reg = <0x80000 0xf80000>;
};
};
};
&mdio {
status = "ok";
ethphy0: ethernet-phy@0 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
ethphy2: ethernet-phy@2 {
status = "ok";
compatible = "ti,dp83867" , "ethernet-phy-ieee802.3-c22";
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
};
ethphy3: ethernet-phy@3 {
status = "ok";
compatible = "ti,dp83867" , "ethernet-phy-ieee802.3-c22";
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
};
};
&dsp0 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp1 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp2 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp3 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp4 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp5 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp6 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&dsp7 {
memory-region = <&dsp_common_memory>;
status = "okay";
};
&gbe_serdes {
status = "okay";
};
#include "k2hk-evm-cmem.dtsi"
#include "keystone-uio.dtsi"
#include "k2hk-uio.dtsi"
Regards,
Snehal
