Hi,
I read the below thread.
https://e2e.ti.com/support/processors/f/791/p/741291/2741356#2741356
It describes as follows;
AM65x is IO coherent with A53 caches, so traffic from any peripheral into MSMC SRAM and DDR is kept coherent with A53 caches.
Yes as long as the data is in MSMC SRAM or DDR. PCIe read will snoop the most recent data as long as the memory page/region is marked outer shared and cacheable in MMU and NBSS registers.
Do you have some code examples of GPMC or PCIe with DMA, which customer can confirm cache coherency ? If possible, TI-RTOS is preferred, but Linux is OK as well.
Since data transaction between memory and peripheral with keeping cache coherency is important for them, they want to evaluate its performance on EVM.
DMA (Data Movement Architecture) on AM65x looks excellent. Do you have any deep dive or training materials for NAVSS, UDMA, UTC, DRA, etc … with more illustrations ?
Thanks and regards,
Hideaki
