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AM6526: TI-RTOS Questions

Joseph Cohen
Prodigy 470 points

Part Number: AM6526

Hello, 

I am working with a customer who has the following questions about the AM6526. 

1)      Can TI-RTOS support SMP mode on the two Cortex-A53s?    I am currently using eCosPRO which supports SMP on Xilinx UltraScale.  I would like TI-RTOS to do the same.

2)      Can TI-RTOS be configure to have tasks as a default to run only on Cortex-A53 CPU0 and specific tasks assigned to run on the other remaining Cortex-A53 CPUx.  I can do this on eCosPro.

3)      Are drivers for the following peripherals available in the SDK for this SOC?

  • Ethernet
  • MCAN
  • MMCSD
  • USB
  • OSPI
  • DMA
  • RTI

4)      Can Ti-RTOS support SMP on the two Cortex-R5Fs?  I would only use them for interfacing to the Ethernet, CAN and Flash.  I would not assign tasks to a particular CPU but let tasks run on both CPUs based on priority.

5)      What is already in SDK for supporting Cortex-R5Fs and the Ethernet, CAN and Flash?    

6)      I am planning to have Cortex-A53 CPU0 to work with the Cortex-R5Fs to interface with Ethernet, CAN and Flash.   I assume SDK will examples on how to do this?

7)      Does TI-RTOS supports the following features?   These are all supported by eCos.

  • OPENSSL
  • USTL
  • POSIX
  • NET SNTP
  • NS_DNTP
  • PPP

8)      How difficult to bring up a simple system based on the above items?

Thank you for your help.

  • 0
    TI__Mastermind 30365 points

    Hi Joseph,

    We will take a look at these questions and get back to you.

    Lali

  • 0
    TI__Mastermind 40620 points

    Hi Joseph, answers below

    A1) Yes, We support SMP mode on A53 cores in BIOS 6.75 as indicated in release notes. There is an UART SMP example for AM65x (cortex A53) in Processor SDK

    • pdk_am65xx_1_0_x\packages\ti\drv\uart\

    A2) Yes, it is possible. There are some details on how to configure RTOS application to run SMP in this SMP-BIOS Wiki. Main idea is to set Task affinity to the core we want to use for a specific task. 

    Example

    • taskParams.affinity = 0 --> runs in core0
    • taskParams.affinity = 1 --> runs in core1

    A3) For available drives, you can check PSDK Device Drivers link.  Below link is for latest RTOS PSDK  AM65x  (06_00_00_07)

    Examples of some of your listed drivers:

    • pdk_am65xx_1_0_x\packages\ti\transport\ndk\nimu\example
    • pdk_am65xx_1_0_x\packages\ti\csl\example\mcan
    • pdk_am65xx_1_0_x\packages\ti\drv\spi\test\ospi_flash

    On the other hand, could you please clarify what flash memory support is your customer looking for?

    A4)  The ARM Cortex R5F doesn`t support SMP mode. R5F cores support Lock-step and split mode operation. Lock-step mode is a diagnostic mode designed for safety where core 1 performs the same compute as core 0 with a clock delay and the output of the two cores is compared to catch any transient errors.  In split mode cores act independently. More information in ARM website:

    https://developer.arm.com/ip-products/processors/cortex-r

    A5) A6) As a starting point, you can check CAN Ethernet Gateway demo available in the PRSDK 6.x.  

    A7) I am aware of POSIX, but I am confirming with the expert the other ones.

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 40620 points

    Hi Joseph, for question 7) we support PPP in NDK and POSIX in RTOS. Other protocols listed are not supported. Just FYI let me refer you to this E2E answered from a colleague with more details on what is supported in NDK.

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Prodigy 470 points

    Hi Paula,

    Thank you for looking into these questions. I appreciate the help! I'm working on getting answers to the questions you asked in your reply.

    One additional question we've received: Can the Linux-RT version also support SMP mode? 

    Thank you,

    Joseph

  • 0 in reply to Joseph Cohen
    TI__Guru** 116980 points

    Joseph,

    Processor SDK Linux and Linux-RT configure the A53 in SMP mode by default. They also support an inmate model that allows for guest application to run as an inmate using the hyper visor mode. For Processor SDK RTOS, since the use case is the best ral time performance the cores are default setup as AMP mode and can optionally be configured to use SMP mode.

    To understand TI RTOS SMP offering please ask your customer to refer the following article:

    http://processors.wiki.ti.com/index.php/SMP/BIOS

    While SMP mode allows for parallel processing using shared cache model and simplifies software design across dual cores in the cluster. There is a drop in interrupt latency and scheduler performance which is critical to some applications. 

    Benchmarks in SMP and AMP mode are described for TI A15 platforms here: (This also applies to A53 clusters)

    http://processors.wiki.ti.com/images/1/14/Public_SmpBiosSlides.pdf

    Regards,

    Rahul