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Question about connect a QVGA 320x240 LCD

WeiJiang
Expert 1080 points 
Dear all,
My board is Dm355 EVM. I want to attach a QVGA(320x240) LCD.

My VPBE used the "PLL1 SYSCLK3" as the module input clock. I don't want
to change the frequency of "ARM subsystem" with "PLL1 SYSCLK1" so I only
can get the "PLL1 SYSCLK3" down to 13.5MHz for the mininum.
Unfortunately, My LCD needs a 5MHz-8MHz DCLK.

I can set the DCLKCTL and DCLKPTN registers to get the required DCLK but
can't get the appropriate Hsync and Vsync. It seems that Hsync and Vsync
is derived from "VPBE module clock" but not the "VCLK(DCLK)".

Did anyone attach 320x240 or 240x320 LCD in the same method? Please help
me, any clue is appreciated!

Wei Jiang
  • TI__Mastermind 37340 points

    This sounds strange as I would image that the same pixel clock (resulting from DLCK settings) would need to drive data rate as well as hsync and vsync.  When you set the DCLK registers above, do you actually see a slower clock ad the VCLK output pin (in an oscilloscope)?

  • in reply to Juan Gonzales
    Expert 1080 points

    hi, Juan,

          I do see a slower VCLK output. You may should set the DCKPW and DCKPTN, But the hsync and vsync never be  slower!

          As HINT is specify the number of ENC clock not the VCLK, I think it's impossible to get the needed Hsync and Vsync if the input VENC clock is too high..

         Now I'm doubting whether I can connect a QVGA LCD with an PLL1SYSCLK3 input clock..

      Wei Jiang

  • in reply to WeiJiang
    TI__Mastermind 37340 points

    Unfortunately, I do not have my hardware with me, but I will look into this when I get back to the office on Monday.

  • in reply to Juan Gonzales
    Expert 1080 points

    Hi, Juan,

           Thanks for ypur kindly reply. By the way, have you gotten the result with your experiment?

         Wei Jiang

  • in reply to WeiJiang
    TI__Mastermind 37340 points

    Wei,

    Unfortunately, I worked off-site today, hence I did not get a chance; I should have said that I would try to get to it this week, depending on my workload.

    Actually, thinking this thru a bit more, I do not have a daughtercard to display LCD output, but I was hoping I could play with registers to see if I can get VCLK, hsync and vsync to change at the same time (will need to verify in an oscilloscope).  Since this will take some time, I need to set aside a good amount of my time to do such experiment and how fast I get to this will depend on how many customers are on my queue tomorrow (FYI, I answer forums part time, but I have other more direct responsabilities)

  • in reply to Juan Gonzales
    Expert 1080 points

    Juan,

          Many thanks[;)]

  • in reply to WeiJiang
    Prodigy 90 points

     Dear Friends,

    Could you attach the 320x240 lcd on your board? I couldn't get correct VDOUT_VCLK. It is still 27Mhz , my LCD needs 6-7Mhz. And also hsync and vsync are also too fast, I made some changes on PLL1Init() in UBL , I set the

    PLL1->PLLDIV3 = 0X8000 | 31; // SYSCLK3

    but it didnt work. Do you have any suggestions?