TDA2SX: adc3101: sample rate is not supported

Suhas,

atl_clkin2=19.2MHz cannot be generated from a DPLL_ABE frequency of 180.6336MHz. I'm not sure why the atl_clkin2 frequency ended up being 20070175, but the requested frequency of 19.2MHz will not be honored as is.

Please set the DPLL_ABE frequency to another frequency such that:

• can be derived from your sysclk using M/N factor
• atl_clkin2=19.2MHz can be generated with an integer divider (i.e. dpll_abe_ck % atl_clkin2 = 0)

Hi Misael,

Thank you for quick response.

Earlier we had set the

&atl {
        assigned-clocks = <&abe_dpll_sys_clk_mux>,
                          <&atl_gfclk_mux>,
                          <&dpll_abe_ck>,
                          <&dpll_abe_m2x2_ck>,
                          <&atl_clkin1_ck>,
                          <&atl_clkin2_ck>;
        assigned-clock-parents = <&sys_clkin1>, <&dpll_abe_m2_ck>;
        assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
                                <11289600>, <11289600>;

        status = "okay";

        atl2 {
                bws = <DRA7_ATL_WS_MCASP2_FSX>;
                aws = <DRA7_ATL_WS_MCASP3_FSX>;
        };
};

and received following as a response; wherein 180633600 is multiple of 11289600

2019-08-12 18:57:48.666] adc3101_set_dai_fmt 17157
[2019-08-12 18:57:48.672] adc3101_set_dai_fmt 64
[2019-08-12 18:57:48.672] davinci-mcasp 48474000.mcasp: SLAVE & MASTER CONFIG 0x4000
[2019-08-12 18:57:48.678] asoc-simple-card sound0: tlv320adc3101-hifi <-> 48474000.mcasp mapping ok
[2019-08-12 18:57:48.682] rate 11025 sysclk 11289473 divs_rate 8000 divs_sysclk 19200000
[2019-08-12 18:57:48.689] rate 11025 sysclk 11289473 divs_rate 44100 divs_sysclk 19200000
[2019-08-12 18:57:48.695] rate 11025 sysclk 11289473 divs_rate 48000 divs_sysclk 19200000

What's the refclk frequency being fed into DPLL_ABE? Typically, sourced from either sys_clk1 or sys_clk2.

The refclk is 20MHz. We have 20MHz crystal for sys_clk1. sys_clk2 is not mounted.

Is there a way to check, if the sys_clk value is set properly?

Yes, please check below debugfs entry:

cat /sys/kernel/debug/clk/sys_clkin1/clk_rate

Likewise, please check rate of other clocks of interest (i.e. dpll_abe_ck, atl_clkin2).

Hi Misael,

Thank you for the quick responses.

We have confirmed that sys_clkin1 is set to 20MHz and dpll_abe_ck is set to 172800000.

Audio mclk is now set to 19.2MHz and we can also see the same on ADC3101 MCLK input.

This has resolved the errors related to invalid clock rate observed during arecord.

However, still there is no MCLK out.

root@dra7xx-evm:~# cat /sys/kernel/debug/clk/mcasp6_ahclkx_mux/clk_rate
19200000
root@dra7xx-evm:~#
root@dra7xx-evm:~# cat /sys/kernel/debug/clk/sys_clkin1/clk_rate
20000000
root@dra7xx-evm:~#
root@dra7xx-evm:~# cat /sys/kernel/debug/clk/mcasp4_ahclkx_mux/clk_rate
19200000
root@dra7xx-evm:~#
root@dra7xx-evm:~# cat /sys/kernel/debug/clk/mcasp7_ahclkx_mux/clk_rate
19200000
root@dra7xx-evm:~#

Also, with arecord, we see below warning;

root@dra7xx-evm:~# arecord -d hw:0,1 -c 2 hw.wav
Recording WAVE 'hw.wav' : Unsigned 8 bit, Rate 8000 Hz, Stasoc_simple_card_hw_params: mclk 0
ereo
rate 8000 sysclk 19200000 divs_rate 8000 divs_sysclk 19200000
 adc3101_hw_params
adc3101_ interface ctrl 64
davinci-mcasp 48474000.mcasp: SLAVE & MASTER CONFIG 0x4000
davinci-mcasp 48474000.mcasp: Too fast reference clock (19200000)
davinci-mcasp 48474000.mcasp: BCLK DIV VAL 75
davinci-mcasp 48474000.mcasp: mcasp mode 0

Same for aplay -

root@dra7xx-evm:~#   aplay -D hw:2,0 -c 2 -t wav -r 44100 -f dat Apna_Time_AayegaWav.wav
Playing WAVE 'Apna_Time_AayegaWav.wav' : asoc_simple_card_hw_params: mclk 0
Signed 16 bit Little Endian, Rate 48000 Hz, Stertlv320aic3x-codec 2-001b: SAMPLING FREQ 48000

Warning: rate is not accurate (requested = 48000Hz, got = 8000Hz)
         please, try the plug plugin
tlv320aic3x-codec 2-001b: CODEC CLK 5120
davinci-mcasp 4846c000.mcasp: SLAVE & MASTER CONFIG 0x4000
davinci-mcasp 4846c000.mcasp: Too fast reference clock (19200000)
davinci-mcasp 4846c000.mcasp: mcasp mode 0

What's MCLK in and MCLK out? Do you see the right rate at J6 pin?

My understanding is that you wanted to have codec as master (McASP as slave). If that's still the case, set the "sound0_master" to the codec node in dts.

The "too fast reference clock" print comes when McASP is in master mode and no McASP internal clock divider can be found for the requested BCLK.

No, we have to configure codec as slave and McASP is master.

Following is the sound0_master node in DTS;

    snd1: sound0 {
        compatible = "simple-audio-card";
        simple-audio-card,name = "DRA7xx-EVM-sound0";
/*
        simple-audio-card,widgets =
            "Headphone", "Headphone Jack",
            "Line", "Line Out",
            "Microphone", "Mic Jack",
            "Line", "Line In";
        simple-audio-card,routing =
            "Headphone Jack",    "HPLOUT",
            "Headphone Jack",    "HPROUT",
            "Line Out",        "LLOUT",
            "Line Out",        "RLOUT",
            "MIC3L",        "Mic Jack",
            "MIC3R",        "Mic Jack",
            "Mic Jack",        "Mic Bias",
            "LINE1L",        "Line In",
            "LINE1R",        "Line In";
*/
               simple-audio-card,widgets =
                       "Line", "Line In";
               simple-audio-card,routing =
                       "IN2_R",                "Line In",
                       "IN3_R",                "Line In",
                       "IN2_L",                "Line In",
                       "IN3_L",                "Line In";
        simple-audio-card,format = "dsp_b";
        simple-audio-card,bitclock-master = <&sound0_master>;
        simple-audio-card,frame-master = <&sound0_master>;
        simple-audio-card,bitclock-inversion;

        sound0_master: simple-audio-card,cpu {
            sound-dai = <&mcasp6>;
            system-clock-frequency = <19200000>;
            system-clock-direction = "out";
        };

        simple-audio-card,codec {
            sound-dai = <&tlv320adc3101>;
/*            clocks = <&atl_clkin2_ck>;     */
            system-clock-frequency = <19200000>;
        };
    };

&atl {
        assigned-clocks = <&abe_dpll_sys_clk_mux>,
                          <&atl_gfclk_mux>,
                          <&dpll_abe_ck>,
                          <&dpll_abe_m2x2_ck>,
                          <&atl_clkin1_ck>,
                          <&atl_clkin2_ck>;
        assigned-clock-parents = <&sys_clkin1>, <&dpll_abe_m2_ck>;
        assigned-clock-rates = <0>, <0>, <172800000>, <361267200>,
                                <11289600>, <19200000>;

        status = "okay";

        atl2 {
                bws = <DRA7_ATL_WS_MCASP2_FSX>;
                aws = <DRA7_ATL_WS_MCASP3_FSX>;
        };
};

Also, from TRM it appears, ABE is not supported in TDA2SX.

Also, with above diagram, it appears, we have to configure the McASP clock to be derived from sys_clkin2. Is this understanding correct?

We do not have crystal connected on sys_clkin2, however can get it mounted.

Will atl_clkin2_ck work for you if not at 19.2MHz?

If so, try the following:

&atl {
        assigned-clocks = <&abe_dpll_sys_clk_mux>,
                          <&atl_gfclk_mux>,
                          <&dpll_abe_ck>,
                          <&dpll_abe_m2x2_ck>,
                          <&atl_clkin1_ck>,
                          <&atl_clkin2_ck>;
        assigned-clock-parents = <&sys_clkin1>, <&dpll_abe_m2_ck>;
        assigned-clock-rates = <0>, <0>, <122880000>, <245760000>,
                                <7680000>, <7680000>;

};

This should work for 8kHz and 48kHz, 16-bits, stereo audio.

Thanks Misael, we already tried this change and could get the errors resolved with aplay and arecord. However there wasn't clockout (mclk) yet. Probably we will check it once in hardware and clock control registers.

Thanks.

Hi Misael,

This setting did not work.

Also, we checked the TRM (sprui29f.pdf for TDA2SX) and there are no references for "atl_clkin2_ck". Could you please check?

 Now we are trying to use, "abe_sys_clk" to see, if that works.

Could you be more specific on what didn't work? You mentioned in a previous post that aplay/arecord errors were gone.

Please share the output of "omapconf show mcasp6" command. omapconf tool can be git-cloned here.

Please refer to the offline discussion on ATL clock in TDA2x device.

Hi Misael,

Configuring the atl_sys_clkin2 did not work. We changed it to "&dpll_abe_ck" appear to be working fine, with all the clocks working.

We are further testing the interface and shall update on same.

Suhas, Any update on testing you have done? Is there anything else needed on this topic?