Part Number: AM3352
Hi,
We're in now in a process of bringing u board on AM3352 processor.
Of a 3 boards that can boot into U-Boot only one is able to boot kernel reliable - two others are stuck at "Starting kernel" and can start only once in a while.
To boot device into kernel, some U-Boom ddr-deffs were changed. We're using one bank M15T1G1664A (www.esmt.com.tw/.../M15T1G1664A(2C).pdf). Current DDR defs are:
/* Oya M15T1G1664A-DEB */
#define M15T1G1664A_IOCTRL_VALUE 0x3BD
#define M15T1G1664A_ZQ_CFG 0x50074BE4
#define M15T1G1664A_EMIF_SDCFG (\
(3 << 29) | /* DDR3 memory */\
(0 << 27) | /* */\
(1 << 24) | /* RQZ/4 */\
(1 << 23) | /* Differential DQS */\
(1 << 21) | /* Dynamic ODT RZQ/4 */\
(0 << 20) | /* Do not disable DDL */\
(1 << 18) | /* Drive strength RZQ/7 */\
(0 << 16) | /* CWL 5 */\
(1 << 14) | /* 16 bit mode */\
(4 << 10) | /* CAS 6 */\
(4 << 7) | /* 13 rows */\
(3 << 4) | /* 8 banks RAM */\
(0 << 3) | /* */\
(2 << 0) /* */\
)
/* Core AC parameters */
#define M15T1G1664A_EMIF_READ_LATENCY 0x100007 /* CL6 + 1*/
#define M15T1G1664A_EMIF_TIM1 0x0888C39B
#define M15T1G1664A_EMIF_TIM2 0x28247FDA
#define M15T1G1664A_EMIF_TIM3 0x501F821F
#define M15T1G1664A_EMIF_SDREF 0x00000C30
#define M15T1G1664A_RATIO 0x80
#define M15T1G1664A_INVERT_CLKOUT 0x0
/* Calculated by software leveling */
#define M15T1G1664A_RD_DQS 0x45
#define M15T1G1664A_PHY_FIFO_WE 0x9A
#define M15T1G1664A_WR_DQS 0x66
#define M15T1G1664A_PHY_WR_DATA 0x90
EMIF parameters was calculated by means of excel spreadsheets that can be found here.
As we didn't have JTAG to run Software leveling from CCS we've used one that can be found via this lin
IOCTRL_VALUE vas found by trial and error method.
With this parameters u-boot mtest runs without errors on all 3 boards. command we were using: mtest 0x80200000 0x87000000
Our boot configuration:
CONTROL: control_status = 0x00400324 * SYSBOOT[15:14] = 01b (24 MHz) * SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing * SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input * SYSBOOT[8] = 0 GPMC CS0 8-bit data bus * Device Type = General Purpose (GP) * SYSBOOT[7:6] = 00b MII (EMAC boot modes only) * SYSBOOT[5] = 1 CLKOUT1 enabled * Boot Sequence : UART0 -> XIP w/WAIT (MUX1) -> MMC0 -> NAND
We have no clues on why it can happen with identical hardware and software.
Maybe there is some parameters we're missing in our setup? Now we have JTAG so we can test something more if possible.
