Part Number: AM3354
According to am335x TRM, GPMC_CLK is from core-PLL(L3S_CLK), PD_PER_L3S_GCLK domain.
The clock can gated, inactive and so on.
I have a few simple questions,
1. was GPMC_CLK a continuous clock or only present when chip-select is LOW (or active)?
2. any suggestions if could not see GPMC_CLK on the pin.
- we are sure that this pin is selected MUX mode and RXACTIVE is set.
