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PRCM

suyash ugare
Prodigy 55 points
Other Parts Discussed in Thread: OMAP3530

 

Dear All,

There are differentt clock configurations available for OMAP3530 in the omap3430_prcm_clock_configs.gel file.

After setting the IIB configuration, the following output is seen:

Putting DPLL into bypass before proceeding
Putting CORE DPLL into bypass before proceeding
Locking CORE DPLL
PRCM clock configuration IIB setup has been completed
SystemClock = 38.4 MHz
DPLL_MULT_VALUE = 284
DPLL_DIV_VALUE = 40
CORE_DPLL_CLK = 531.98 MHz
CORE_CLK = 265.99 MHz
L3_CLK = 132.995 MHz

Can anybody help me in understanding what each of the above parameters/registers mean?
What is each of the frequency referring to?

Thanks

 
  • 0
    TI__Guru* 86060 points

    These values are described in the PRCM chapter of the TRM. 

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 55 points

    Thank you James.

    As per the TRM, In OMAP3530, the IVA2.2  subsystem is fed by the IVA2_CLK.
    And the System Control (SYSC) unit, inside IVA22.2 subsystem, will generate the CD0_CLK, CD1_CLK, and CD2_CLK using IVA2_CLK..

    I could not get the answer to the following :
    A] What is the relation between CD0_CLK and the IVA2_CLK ?

    B] How is the CD0_CLK, software configurable clock, configured using the register PRCM.CM_CLKSEL1_PLL_IVA2 and
    PRCM.CM_CLKSEL2_PLL_IVA2 ?

    CD1_CLK and CD2_CLK are divide by 2 of CD0_CLK

     

    Regards,

    Suyash

  • 0 in reply to suyash ugare
    TI__Guru* 86060 points

    CD0_CLK is just the gated version of IVA2_CLK.  They are the same frequency when DM_FCLKEN_IVA2 is enabled.  Refer to the flowchart "Processor Clock Basic Programming Model" to configure this clock.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 55 points

    What does this frequency - IVA2_DPLL_FREQSEL control?

    Does this come into existence  when the CM_FCLKEN_IVA2 is disabled?

     

    Regards,

    Suyash