TMS320C6657: Several questions about Timer, Reset, Boot Mode and so on.

Jonathan,

I have looped in our HW design experts to add input but I will try to attempt to respond to as many questions based on my previous experience booting and reset with customer board designs 

Jonathan Lee89 said:

1. About Timer with TMS320C6657 EVM

Q1-1 : When we look at the TMS320C6657 EVM, It seems to me that DSP_TIMI[0:1] take input 24Mhz clock from the FPGA. Is it reference clock for DSP Timer?

Q1-2 : What is mandatory input clock to use DSP Internal Timer? Is it possible to use of external OSC instead of FPGA?

Q1-3 : What is the purpose of DSP_TIMO[0:1] in the EVM ?

Yes, this detail is called out in the C6657 EVM TRM document as you can see here :

https://www.einfochips.com/wp-content/uploads/2016/04/C6657-Lite-EVM_TechnicalReferenceManual.pdf

The timing supported by this pin is found in the C6657 datasheet#mce_temp_url# in Timer Electrical Data and timing section 5.7.14

An external OSC can`t be used in place of FPGA like timing controller for this pin. Please note that the Pin has three functions muxed into it. GPIO, Timer input and BootMODE pins. At the time of boot the pin is used to set boot mode pin and then can be switched to timer input. Putting a OSC on it may cause unstable behavior in the bootROM.

TIMOx pins are provided to connect timer output from the chip to external components for reference or the pins have secondary functionality to act as GPIO pins. Best way to read the purpose of the pins is to locate the pin name on C665x from Schematic and search in the device data manual for example these pins are AC19 and AE20.

Jonathan Lee89 said:

2. About Reset operation with TMS320C6657 EVM. 

Q2-1 : We don't want to use FPGA for RESET#, POR#, RESETFULL# signal. Could you let me know how to control those signal in what signal?

Q2-2 : Could you recommend the best way to control the RESET# signal without using FPGA?

The RESET#, POR#, RESETFULL# signal pins require timing control for implementation of power up and power down sequence as you can see in the C6657 EVM Technical reference manual. In addtion to that document,please ask the customer to refer to the Hardware Design guide for Keystone Devices:
https://www.integretek.com/wp-content/uploads/2016/11/HW-Design-Guide-For-Keystone-Devices-sprabi2b.pdf 

The FPGA in the EVM Design is like the board controller that enabled us to implement boot, clock, reset , external FPGA connect and other such functionalities. You don`t need to use an expensive FPGA to design this power/reset sequencing. The same can also be designed using a low cost MCU circuitry as our design for Keystone II EVMs demonstrate. Please refer to K2G EVM design for reference where this is implemented with use of FPGA.

http://www.ti.com/tool/EVMK2G#technicaldocuments

Q3-1 : We don't want to use IBL. In this case, as far as we are aware, we should revise built-in ROM boot-loader. Could you let me know what S/W changes must be made in this case?

Q3-2 : There are several chip select (CS0~CS5) for external device. Which one should I use for NOR Flash Boot?

Q3-3 : As far as we are aware, the I2C EEPROM is used to IBL-Booting in TMS320C6657 EVM. What data(information) does EEPROM have?

Q3-4 : If we are designing as IBL booting, do we have to configure Boot Device to I2C Master?

IBL is not mandatory to boot on C665x devices. This was introduced on the EVM design as a safety net to  work around errata issues and for supporting booting mechanism that are not natively supported in the device ROM bootloader (fixed in L2 ROM memory). We have tested SPI and NAND boot without IBL on the C6657 EVM and have provided the examples for reference in the article C66x Bootloader examples without IBL

Not sure where you are seeing CS0 to CS5. The device datasheet shows pins EMIFCE0 to EMIFCE3  (They are also referred to as EMIF_CS2 to EMIFCS5). We recommend using EMIFCE0 / EMIF_CS2. Check the EMIF16 boot Mode section in the device Data manual 

We don`t have EMIF16 NOR On the EVM but have validated the boot mode on an internal validation platform that is used for silicon wakeup which has the full feature set. The EMIF16 NOR writer and some critical guidance can be found on this boot mode in the article EMIF16 NOR boot 

The way the EVM boot is designed using the Processor SDK RTOS based software, the I2C EEPROM has secondary bootloader software that allows users to setup DDR memory and setup device initialization that is not natively supported in the ROM or implement work around for boot modes that rely on serdes setup .  I2C EEPROM also provides developers the ability to provide alternate boot parameter tables that changes ROM default settings used to setup the boot media/PLL, etc. 

Yes, when implementing IBL booting, the HW needs to be setup for I2C Master boot. You can also refer to EVM boot switch setting for reference.

http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#boot-mode-dip-switch-settings

Jonathan Lee89 said:

4. About Configuration bootmode with TMS320C6657 EVM

Q4-1 : We have designed our customized board based on TMS320C6657 EVM as can be seen attached schematic. Boot Device configuration pin is BOOTMODE[3:0], right?

Q4-2 : What does PLL Multiplier signify? Does that mean CORECLK?

The description of Boot MODE pins are provided in the DEVSTAT register description in the Device data manual (section 6.28). Boot device setting for this mode is provided in BOOTMODE[5:0]. BOOTMODE[2:0] decides the boot device and the BOOTMODE[5:3] decides the sub module (EMIF16 in this case)

PLL Config settings is described in detail  in section 6.29 of the Device data manual. These pins indicate to the ROM what in the input clock used in your HW design so that the ROM can read the Device speed setting and configure the multiplier and divider values for the device PLLs when setting up the boot. Here is the table for your reference. Please set BOOTMODE[12:10] accordingly

Jonathan Lee89 said:

5. About Boot Strap Configuration. 

Q5-1: When using EMIF16 NAND Flash for booting, how do I set the Boot Strap Configuration for above schematic.
(Coreclk : 50MHz, DDRCLK : 50MHz, PCIE Unused)

Q5-2 : When using EMIF16 NOR Flash(32MB) for booting, how do I set the Boot Strap Configuration for above schematic? 

(Coreclk : 50MHz, DDRCLK : 50MHz, PCIE Unused)
Case 1 : If we are using IBL booting...
Case 2 : if we are not using IBL booting...

The PLL configuration during boot only relates to Main PLL setup. For DDR PLL configuration there is a software structure defined that can be appended to the boot image to configure the DDR PLL. If you are using the secondary bootloader like IBL then you can control all of DDR PLL configuration and the EMIF initialization in the secondary boot code. 

There is a mismatch in the PLL setting in the schematic and what you have posted in your question. Since  BOOTMODE[ 12: 10] =011, I was assuming the SYSCLK used to setup core clock is 100 MHz but you indicated that the coreclk is 50 MHz. Please check that setting. The Switch setting for EMIF NAND is part of the document that shows direct booting from NAND. If your custom board design reuses the C6657 EVM design, then for EMIF NAND as we used on the EVM.

IBL booting doesn`t support EMIF NOR so there is no need to use IBL settings here. You can look at the GEL file that we used in the past to setup EMIF16 NOR boot on the EVM for reference. I believe this sets the DEVSTAT to 0x21 

evmc66x_emif16_boot.gel

Regards,

Rahul