AM5728: Fvid2_start problem

Andrei Kolganov

Part Number: AM5728
Other Parts Discussed in Thread: SYSBIOS, , AM5708, TMS320C6678

My project uses VIP on board AM572X EWM. After power on from SD card A15 boots MLO. Then MLO starts C66 which configurates FVID2 drivers. When I start C66 in baremetal FVID2 works. But when I start C66 under RTOS FVID2 stops on the FVID2_start(). The problem is like https://e2e.ti.com/support/processors/f/791/t/783033?RTOS-AM5728-boot-from-sd-card-and-the-app-stopped-at-Fvid2-start-. The update of PDK to the version of 1_0_15 didn't do any results. What is the solution of this problem? Please help me!

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

Can you try this if helps? https://e2e.ti.com/support/processors/f/791/t/814725

Regards, Eric

0 Andrei Kolganov over 6 years ago in reply to lding

Intellectual 275 points

Hi lding,

As I wrote you earlier, I have two version of program for C66: baremetal and RTOS version. In both cases I use the same version of MLO for A15. In app I use the similar initialization sequence of FVID2. In case of baremetal design I have the video capture. In RTOS case the program failed after calling FVID2_start() and it doesn't even return error code. May be I make the wrong configuration of RTOS?

//------------------------------------------------------------------------------------------------------------------------------------------------------
void setup_VIP(void)
{
Int32 retVal = FVID2_SOK;
Vps_InitParams vpsInitPrms;
Uint32 tmp32;
Uint32 cookie;

#ifdef DEBUG_PRINT
//UART_printf("VIP Setup Started...\n");
UART_puts("VIP Setup Started...\n", -1);
#endif

g_byWritten = 0;

cookie = BspOsal_disableInterrupt();
tmp32 = HW_RD_REG32(0x4A002960); // CTRL_CORE_DSP1_IRQ_44_45
HW_WR_REG32(0x4A002960, (tmp32 & 0x0000FFFF) | 0x01600000); // set INT352 (VIP2) to IRQ_CROSSBAR CTRL_CORE_DSP1_IRQ_44_45 IRQ45
BspOsal_restoreInterrupt(cookie);

VIPClocksAndPinMuxSetup();

retVal = Fvid2_init(NULL);
if (BSP_SOK != retVal)
{
UART_printf("Error: FVID2 Init failed!!\r\n");
return;
}
#ifdef DEBUG_PRINT
UART_printf("FVID2 Init Completed\n");
#endif

VpsInitParams_init(&vpsInitPrms);

/* Pass the interrupt numbers from application for VPS instances.
* setting same interrupt numbers as in default setting for referance.
* Specifying for all instances, only applicable instances are used by lib.
* Driver will only register for the specified interrupt numbers.
* The corresponding crossbar mapping for the device interrupt should be
* done by the application. In the Vps examples the crossar mapping is
* done from function Bsp_platformTda2xxInit/Bsp_platformTda3xxInit.
* Application may pass the Bsp_PlatformInitParams->isIrqXBarSettingReq as
* false to Bsp_platformInit function and do all the crossbar mapping
* required or update the crossbar configuration done in
* Bsp_platformTda2xxInit/Bsp_platformTda3xxInit.
*/

vpsInitPrms.irqParams.vipIrqNum[1U] = CSL_INTC_EVENTID_VIP2INT0;

retVal = Vps_init(&vpsInitPrms);
if (BSP_SOK != retVal)
{
UART_printf("Error: VPS Init failed!!\r\n");
return;
}
#ifdef DEBUG_PRINT
UART_printf("VPS Init Completed\n");
#endif

retVal = BspUtils_memInit();
if (BSP_SOK != retVal)
{
GT_0trace(BspAppTrace, GT_ERR, "Error: App MEM Utils Init failed!!\r\n");
UART_printf("Error: App MEM Utils Init failed!!\r\n");
}

/* Create global capture handle, used for common driver configuration */
fvidHandleAll = Fvid2_create(FVID2_VPS_CAPT_VID_DRV, VPS_CAPT_INST_ALL,
NULL, /* NULL for VPS_CAPT_INST_ALL */
NULL, /* NULL for VPS_CAPT_INST_ALL */
NULL); /* NULL for VPS_CAPT_INST_ALL */
if (fvidHandleAll == NULL)
{
UART_printf("Global Handle Create Failed!\r\n");
return;
}

#ifdef DEBUG_PRINT
UART_printf("Create Capture Video Driver - DONE !\r\n");
#endif

//--------------------
initCaptParams();
//--------------------

drvHandle = Fvid2_create(FVID2_VPS_CAPT_VID_DRV, VPS_CAPT_VIP_MAKE_INST_ID(VPS_VIP2, VPS_VIP_S0, VPS_VIP_PORTA)/*g_instId*/,
&instObj.createParams, &instObj.createStatus, &instObj.cbParams);
if ((drvHandle == NULL) || (instObj.createStatus.retVal != FVID2_SOK))
{
UART_printf("Capture Create Failed!!!\r\n");
retVal = instObj.createStatus.retVal;
return;
}

if (FVID2_SOK == retVal)
{
retVal = Fvid2_control(drvHandle, IOCTL_VPS_CAPT_SET_VIP_PARAMS, &instObj.captParams, NULL);//////////////////////////

if (retVal != FVID2_SOK)
{
UART_printf("VIP Set Params IOCTL Failed!!!\r\n");
Fvid2_delete(drvHandle, NULL);
return;
}
#ifdef DEBUG_PRINT
UART_printf("Fvid2_control Success\n");
#endif
}
if (retVal == FVID2_SOK)
{
retVal = allocAndQueueFrames();
if (retVal != FVID2_SOK)
{
UART_printf("Capture Alloc and Queue Failed!!!\r\n");
return;
}
#ifdef DEBUG_PRINT
UART_printf("allocAndQueueFrames Success\n");
#endif
}

/* Start capture */
retVal = Fvid2_start(drvHandle, NULL);
if(retVal == FVID2_SOK)
{
#ifdef DEBUG_PRINT
UART_printf("Starting capture ...\r\n");
UART_printf("Capture in progress ... DO NOT HALT!\n");
#endif
}
else
{
UART_printf("Capture Failed!\r\n");
}
}

0 lding over 6 years ago in reply to Andrei Kolganov

TI__Guru* 95265 points

Hi,

Sorry for the late response! There are baremetal case VPS loopback example and VPS loopback baremetal examples. I compared them there is no substantial differences, the former has .cfg file, SYSBIOS/XDC header inclusion and task functions. The latter just use the SYSBIOS code in a baremetal way, there is no re-written for any API or test application code. I knew both examples are tested and worked. Did you verify both worked in CCS/JTAG environment at your side, then use boot loader (MLO)? This will establish a work base that SYSBIOS application worked.

For your case, you also have the baremetal one and SYSBIOS one, I assume you used almost the same code, correct? When you ran them standalone on C66x with JTAG/CCS, did both work for capture?

When using MLO, one thing you need to make sure is the MLO memory is not overlapped with the application. When boot from MLO, you can add a global volatile variable at the beginning of main(), like:

volatile unsigned int flag = 1;

while (flag);

So the code should spin here when jumped into main() application, then you connect the JTAG/CCS and load the symbol, then poke the memory of flag to 0, you can step through the code why FVID2_start() stuck?

Regards, Eric

0 Andrei Kolganov over 6 years ago in reply to lding

Intellectual 275 points

Hi,

Actualy, my apps isn't VPS loopback examples. My apps is based on this examples. It's difficult to me to start app without MLO as MLO include initial setup for video sensor and serializer and other peripheral. That is the structure of my app. Setup procedure consists of separate functions of setup of AM5728EVM. In MLO I tried to take only necessary parts of example. So I try to porting software from EVM to my board. In case of JTAG-debugging I have the same result as load from SD card. When using JTAG I don't see what is happening inside FVID2 libs when C66 jumps into FVID2_start()

From the moment of calling FVID2_start() program counter (PC) doesn't match with highlighted line. Probably it happens because of the compile FVID2 libs with optimization.

As for the memory overlapping MLO and app areas I used the same address spaces for baremetal and RTOS versions. It's their map files:

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

OUTPUT FILE NAME: <_C66_BareMetal_AM5728_EVM_PDK_1_0_14.out>

ENTRY POINT SYMBOL: "_c_int00" address: 8006fac0

MEMORY CONFIGURATION

name origin length used unused attr fill

---------------------- -------- --------- -------- -------- ---- --------

L2_ROM 00000000 00004000 00000000 00004000 RWIX

RST_START 00800000 00000300 00000220 000000e0 RWIX

IRAM_MEM 00800300 00007c00 00000000 00007c00 RWIX

L2_RAM 20000000 00010000 00000000 00010000 RWIX

OCMC_RAM1 40300000 00080000 00000000 00080000 RWIX

OCMC_RAM2 40400000 00100000 00000000 00100000 RWIX

OCMC_RAM3 40500000 00100000 00000000 00100000 RWIX

APP_CODE_MEM 80001000 001ff000 00090371 0016ec8f RWIX

APP_CACHED_DATA_MALLO 80200000 04000000 04000000 00000000 RWIX

APP_CACHED_DATA_MEM 84200000 08000000 01dd360c 0622c9f4 RWIX

APP_CACHED_DATA_BLK1_ 8c200000 0fe00000 00000000 0fe00000 RWIX

APP_CACHED_DATA_BLK2_ 9c000000 08000000 00000000 08000000 RWIX

APP_UNCACHED_DATA_BLK a4000000 00200000 0001d4c0 001e2b40 RWIX

SEGMENT ALLOCATION MAP

run origin load origin length init length attrs members

---------- ----------- ---------- ----------- ----- -------

00800000 00800000 00000220 00000220 r-x

00800000 00800000 00000220 00000220 r-x .csl_vect

80001000 80001000 00090388 00090388 r-x

80001000 80001000 00070ec0 00070ec0 r-x .text

80071ec0 80071ec0 00006b18 00006b18 r-- .const.1

800789e0 800789e0 00007778 00007778 r-- .const.2

80080160 80080160 0000fb29 0000fb29 r-- .const.3

8008fc90 8008fc90 000016f8 000016f8 r-- .cinit

84200000 84200000 01dd2cd8 00000000 rw-

84200000 84200000 01dcd9dc 00000000 rw- .far

85fcd9e0 85fcd9e0 000042f4 00000000 rw- .fardata

85fd1cd8 85fd1cd8 00000800 00000000 rw- .stack

85fd24d8 85fd24d8 00000800 00000000 rw- .sysmem

85fd2cd8 85fd2cd8 0000075c 0000075c r--

85fd2cd8 85fd2cd8 0000075c 0000075c r-- .switch

85fd3438 85fd3438 000001e0 00000000 rw-

85fd3438 85fd3438 00000120 00000000 rw- .cio

85fd3558 85fd3558 0000005e 00000000 rw- .bss

85fd35b8 85fd35b8 00000060 00000000 rw- .neardata

a4000000 a4000000 0001d4c0 00000000 rw-

a4000000 a4000000 0001d4c0 00000000 rw- .bss:extMemNonCache:vpdma

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

OUTPUT FILE NAME: <_C66_BIOS_AM5728_EVM_PDK_1_0_15.out>

ENTRY POINT SYMBOL: "_c_int00" address: 80072d60

MEMORY CONFIGURATION

name origin length used unused attr fill

---------------------- -------- --------- -------- -------- ---- --------

L2_ROM 00000000 00004000 00000000 00004000 RW X

RST_START 00800000 00000300 00000000 00000300 RW X

IRAM_MEM 00800300 00007c00 00000000 00007c00 RW X

L2_RAM 20000000 00010000 00000000 00010000 RW X

OCMC_RAM1 40300000 00080000 00000000 00080000 RW X

OCMC_RAM2 40400000 00100000 00000000 00100000 RW X

OCMC_RAM3 40500000 00100000 00000000 00100000 RW X

APP_CODE_MEM 80001000 001ff000 000784a0 00186b60 RW X

APP_CACHED_DATA_MALLO 80200000 04000000 00000000 04000000 RW X

APP_CACHED_DATA_MEM 84200000 08000000 00e4f442 071b0bbe RW X

APP_CACHED_DATA_BLK1_ 8c200000 0fe00000 0f200000 00c00000 RW X

APP_CACHED_DATA_BLK2_ 9c000000 08000000 00000000 08000000 RW X

APP_UNCACHED_DATA_BLK a4000000 00200000 0001d4c0 001e2b40 RW X

DDR_MEM_256M b0000000 10000000 00000000 10000000 RW X

SEGMENT ALLOCATION MAP

run origin load origin length init length attrs members

---------- ----------- ---------- ----------- ----- -------

80001000 80001000 000782a0 000782a0 r-x

80001000 80001000 000782a0 000782a0 r-x .text

80079400 80079400 00000200 00000200 r-x

80079400 80079400 00000200 00000200 r-x .vecs

84200000 84200000 00e22f5c 00000000 rw-

84200000 84200000 00e22f5c 00000000 rw- .far

85022f60 85022f60 0002040a 0002040a r--

85022f60 85022f60 0002040a 0002040a r-- .const

85043370 85043370 000097c8 00000000 rw-

85043370 85043370 000057c4 00000000 rw- .fardata

85048b38 85048b38 00004000 00000000 rw- .stack

8504cb38 8504cb38 00000720 00000720 r--

8504cb38 8504cb38 00000720 00000720 r-- .switch

8504d258 8504d258 000001b0 00000000 rw-

8504d258 8504d258 00000120 00000000 rw- .cio

8504d378 8504d378 0000000a 00000000 rw- .bss

8504d388 8504d388 00000080 00000000 rw- .neardata

8504d408 8504d408 00002048 00002048 r--

8504d408 8504d408 00002048 00002048 r-- .cinit

a4000000 a4000000 0001d4c0 00000000 rw-

a4000000 a4000000 0001d4c0 00000000 rw- .bss:extMemNonCache:vpdma

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

I remind that MLO with system's setup is the same for baremetal and RTOS cases. So there was memory overlapping in both cases, right?

0 lding over 6 years ago in reply to Andrei Kolganov

TI__Guru* 95265 points

Hi,

Thanks for the explanation! TI MLO uses OCMC memory, your APP uses DDR or a small portion of L2, I don't see that MLO overlapping with APP. Some questions:

1. You didn't use any TI VPS test example code, instead you wrote your code called void setup_VIP(void), what TI source code you referred to for this?

2. Did you establish a working baseline that using TI MLO+APP it worked? At the beginning of this thread, I pointed a link with solution verified by several customers.

3. "Setup procedure consists of separate functions of setup of AM5728EVM. In MLO I tried to take only necessary parts of example" Do you use TI MLO as it is, or you did some customization inside MLO?

4. Test is done on TI EVM or your own board?

5. What is the Processor SDK RTOS release used? I saw C66_BareMetal_AM5728_EVM_PDK_1_0_14.out and _C66_BIOS_AM5728_EVM_PDK_1_0_15.out?

6. Is the same setup_VIP(void) code you used for build bare-metal application and SYSBIOS application?

7. Is bare metal application always worked on CCS/JTAG alone or using MLO to boot?

8. For the SYSBIOS application, you need to re-build the fvid2 library without optimization if you can't step into the library code.

Regards, Eric

0 Andrei Kolganov over 6 years ago in reply to lding

Intellectual 275 points

1. I referred to CaptureVip and loopbackBareMetal examples. I wrote my own initialization of video sensor and SerDes and use it in MLO for A15. For boot speed up I modified original TI's code for using of only one stream.

2. As for the clock source CM_CAM_VIP2_CLKCTRL = 0x00000001 at the begining of calling FVID2_start().

3. MLO consists the main system's setup + full video source setup . In the result of loading MLO we have video stream on VIN3A of AM5728.

uint32_t oppMode = OPP_MODE_NOM;

#if defined(OPP_HIGH)

boardCfg = BOARD_INIT_PLL_OPP_HIGH;

oppMode = OPP_MODE_HIGH;

#elif defined(OPP_OD)

boardCfg = BOARD_INIT_PLL_OPP_OD;

oppMode = OPP_MODE_OD;

#elif defined(OPP_NOM)

boardCfg = BOARD_INIT_PLL_OPP_NOM;

oppMode = OPP_MODE_NOM;

#endif

boardCfg |= BOARD_INIT_UNLOCK_MMR |

BOARD_INIT_MODULE_CLOCK |

BOARD_INIT_PINMUX_CONFIG |

BOARD_INIT_DDR |

BOARD_INIT_WATCHDOG_DISABLE;

/* Configure AVS voltage for the selected OPP to the voltage rails. */

SBL_Configure_AVS(oppMode);

/* Board Library Init. */

Board_init(boardCfg);

…

/// UART

UART_Params_init(&params);

params.writeDataMode = UART_DATA_BINARY;

params.baudRate = 3000000;

UART_stdioInit2(2 /*BOARD_UART_INSTANCE*/, &params);

/// End of UART

UART_printf("\n\nA15 START...\n");

…

/* enable clocks for slave core modules. */

SBL_SlaveCorePrcmEnable();

UART_printf("A15: %s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);

/* Image Copy */

SBL_ImageCopy(&evmAM572xEntry);

/* Cache Write back after image copy to ensure the slave cores are brought

** out of reset correctly.

CSL_a15WbAllDataCache();

if (evmAM572xEntry.entryPoint_DSP1 != 0)

{

UART_printf("A15: Start MPU_DSP1...[%08X]\n", evmAM572xEntry.entryPoint_DSP1);

/* Release the DSP1 core out of reset */

SBL_DSP1_BringUp(evmAM572xEntry.entryPoint_DSP1);

}

4. Test is failed at FVID2_start() on both AM5728EVM and my own board based on AM5708.

5. At this time I use PDK_1_0_15. Although PDK_1_0_14 give the same bad result.

6. The differences are minimal: in BIOS version added one extra function BspUtils_memInit()

7. In baremetal configuration the system boot from SD-card without JTAG and it's ok.

8. I don't have any experience of rebuild parts of PDK and I'm warning of unexpected changes in PDK. Could you provide me with the compiled FVID2 lib files or give me instructions how to compile it? If I think right I need to use

c:\ti\pdk_am57xx_1_0_15\packages\ti\drv\vps\src\fvid2\makefile ?

Regards, Andrei

0 lding over 6 years ago in reply to Andrei Kolganov

TI__Guru* 95265 points

Hi,

Please refer to http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_overview.html#building-the-sdk, section 1.4.5. Rebuilding Components. the command would be like this:

C:\ti\pdk_[soc]_[version]\packages>gmake vps

You can add LIMIT_BOARDS="<BOARD>" LIMIT_SOCS="<SOC>" LIMIT_CORES="<CORE>" to further reduce the time. This will build the release libraries with optimization. And the VPS application is always linked with release libraries.

So, you have to change the build rules: C:\ti\pdk_am57xx_1_0_15\packages\ti\build\makerules\rules_66.mk BEFORE you issue above command.

# CFLAGS based on profile selected
ifeq ($(BUILD_PROFILE_$(CORE)), debug)
CFLAGS_INTERNAL +=
CFLAGS_XDCINTERNAL = -Dxdc_target_name__=C66 -D_DEBUG_=1
ifndef MODULE_NAME
CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_HFILE_NAME)_pe66.h'
endif
LNKFLAGS_INTERNAL_BUILD_PROFILE =
endif

ifeq ($(BUILD_PROFILE_$(CORE)), release)
LNKFLAGS_INTERNAL_BUILD_PROFILE =
# CFLAGS_INTERNAL += -o3 --optimize_with_debug

CFLAGS_XDCINTERNAL = -Dxdc_target_name__=C66 -D_DEBUG_=1
ifndef MODULE_NAME
CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_HFILE_NAME)_pe66.h'
endif

Change the "release" CFLAGS_INTERNAL as the "debug", then you should be able to build a release library as a debug library. Then step into it when FVID2 stuck.

Regards, Eric

0 Andrei Kolganov over 6 years ago in reply to lding

Intellectual 275 points

Hi Eric,

I found source of stuck:

it's function BspOsal_sleep(). Also function Osal_delay() caused system's stop in another parts of RTOS program. In baremetal design these functions works correctly. It's seems like some initializations is absent in RTOS version.

I can't debug Task_sleep function, because this is part of the optimized RTOS-kernel.

0 lding over 6 years ago in reply to Andrei Kolganov

TI__Guru* 95265 points

Hi,

Thanks for the debug! It looks that the timer is not enabled in the SYSBIOS. In this case, if you add a task_sleep() at the beginning of the main(), it will stuck there as well, correct? I am not sure which timer is used by SYSBIOS as heart beat, one way is to enable all the timer's PRCM domain. This code you can refer to the GEL file at ccs_base\emulation\boards\am572x\gel\AM572x_prcm_config.gel, function AM572x_PRCM_Module_AllEnable_Config(). This may be tedious.

Are you able to attach the .cfg file for the SYSBIOS application? I also asked the BIOS colleague to check what timer needs to be enabled.

Regards, Eric

0 Andrei Kolganov over 6 years ago in reply to lding

Intellectual 275 points

Hi Eric,

Yes, that's right. When I added a task_sleep() in main() the program was stuck. Then I added in my program AM572x_PRCM_Module_AllEnable_Config() from ccs_base\emulation\boards\am572x\gel\AM572x_prcm_config.gel and there was no effect.

/* PRCM clock domain state setting functions */
prcm_set_clkdomain_state(CAM_CM_CORE, CAM_CM_CORE__CM_CAM_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER2_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(L3INIT_CM_CORE, L3INIT_CM_CORE__CM_L3INIT_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(L3INIT_CM_CORE, L3INIT_CM_CORE__CM_GMAC_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(CORE_CM_CORE, CORE_CM_CORE__CM_EMIF_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(CORE_CM_CORE, CORE_CM_CORE__CM_DMA_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(CORE_CM_CORE, CORE_CM_CORE__CM_IPU2_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(COREAON_CM_CORE, COREAON_CM_CORE__CM_COREAON_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(DSS_CM_CORE, DSS_CM_CORE__CM_DSS_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU1_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(RTC_CM_CORE_AON, RTC_CM_CORE_AON__CM_RTC_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(VPE_CM_CORE_AON, VPE_CM_CORE_AON__CM_VPE_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(MPU_CM_CORE_AON, MPU_CM_CORE_AON__CM_MPU_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(DSP1_CM_CORE_AON, DSP1_CM_CORE_AON__CM_DSP1_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(DSP2_CM_CORE_AON, DSP2_CM_CORE_AON__CM_DSP2_CLKSTCTRL, SW_WKUP );
prcm_set_clkdomain_state(IVA_CM_CORE, IVA_CM_CORE__CM_IVA_CLKSTCTRL, SW_WKUP );

/* PRCM Generic module mode setting functions */
prcm_set_module_mode(CAM_CM_CORE, CAM_CM_CORE__CM_CAM_VIP1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CAM_CM_CORE, CAM_CM_CORE__CM_CAM_VIP2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CAM_CM_CORE, CAM_CM_CORE__CM_CAM_VIP3_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_DMA_DMA_SYSTEM_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_EMIF_DMM_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_EMIF_EMIF1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_EMIF_EMIF2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_EMIF_EMIF_OCP_FW_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3INSTR_L3_MAIN_2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_GPMC_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_L3_MAIN_1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_MMU_EDMA_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_MMU_PCIESS_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_OCMC_RAM1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_OCMC_RAM2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_OCMC_RAM3_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_OCMC_ROM_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_TPCC_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_TPTC1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L3MAIN1_TPTC2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_L4_CFG_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX10_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX11_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX12_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX13_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX3_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX4_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX5_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX6_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX7_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX8_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_MAILBOX9_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(CORE_CM_CORE, CORE_CM_CORE__CM_L4CFG_SPINLOCK_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
/*
prcm_set_module_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_MCASP1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
*/
prcm_set_module_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_TIMER5_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_TIMER6_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_TIMER7_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU_TIMER8_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L3INIT_CM_CORE, L3INIT_CM_CORE__CM_L3INIT_MMC1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L3INIT_CM_CORE, L3INIT_CM_CORE__CM_L3INIT_MMC2_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L3INIT_CM_CORE, L3INIT_CM_CORE__CM_GMAC_GMAC_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER2_L4_PER2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_L4_PER3_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_TIMER13_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_TIMER14_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_TIMER15_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER3_TIMER16_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO2_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO3_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO4_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO5_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO6_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO7_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_GPIO8_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_I2C1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_I2C2_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_I2C3_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_I2C4_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_L4_PER1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_MCSPI1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_MMC3_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_MMC4_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER10_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER11_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER2_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER3_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER4_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_TIMER9_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER2_QSPI_CLKCTRL, MODE_ENABLED, 0x05000000, 0x07000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_UART1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER_UART3_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(MPU_CM_CORE_AON, MPU_CM_CORE_AON__CM_MPU_MPU_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(VPE_CM_CORE_AON, VPE_CM_CORE_AON__CM_VPE_VPE_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_GPIO1_CLKCTRL, MODE_AUTO, 0x00000000, 0x00000000 );
prcm_set_module_mode(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_TIMER1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_TIMER12_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_WD_TIMER1_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );
prcm_set_module_mode(WKUPAON_CM, WKUPAON_CM__CM_WKUPAON_WD_TIMER2_CLKCTRL, MODE_ENABLED, 0x00000000, 0x00000000 );

/* PRCM Specialized module mode setting functions */
prcm_set_proc_mode(IVA_CM_CORE, IVA_CM_CORE__CM_IVA_SL2_CLKCTRL, MODE_AUTO );
prcm_set_proc_mode(IVA_CM_CORE, IVA_CM_CORE__CM_IVA_IVA_CLKCTRL, MODE_AUTO );
prcm_set_proc_mode(CORE_CM_CORE, CORE_CM_CORE__CM_IPU2_IPU2_CLKCTRL, MODE_AUTO );
prcm_set_dss_mode(DSS_CM_CORE, DSS_CM_CORE__CM_DSS_DSS_CLKCTRL, MODE_ENABLED );
prcm_set_ipu1_mode(IPU_CM_CORE_AON, IPU_CM_CORE_AON__CM_IPU1_IPU1_CLKCTRL, MODE_AUTO );

My current .cfg file:

var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Diags = xdc.useModule('xdc.runtime.Diags');
var Error = xdc.useModule('xdc.runtime.Error');
var Log = xdc.useModule('xdc.runtime.Log');
var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
var Main = xdc.useModule('xdc.runtime.Main');
var SysStd = xdc.useModule("xdc.runtime.SysStd");
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
var Ecm = xdc.useModule ('ti.sysbios.family.c64p.EventCombiner');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var Timer = xdc.useModule('ti.sysbios.hal.Timer');
var Swi = xdc.useModule('ti.sysbios.knl.Swi');

/*
* Uncomment this line to globally disable Asserts.
* All modules inherit the default from the 'Defaults' module. You
* can override these defaults on a per-module basis using Module.common$.
* Disabling Asserts will save code space and improve runtime performance.
Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
*/

/*
* Uncomment this line to keep module names from being loaded on the target.
* The module name strings are placed in the .const section. Setting this
* parameter to false will save space in the .const section. Error and
* Assert messages will contain an "unknown module" prefix instead
* of the actual module name.
Defaults.common$.namedModule = false;
*/

/*
* Minimize exit handler array in System. The System module includes
* an array of functions that are registered with System_atexit() to be
* called by System_exit().
*/
System.maxAtexitHandlers = 4;

/* Disable cache for 0xA0000000 through 0xBFFFFFFF area */
Cache.setMarMeta(0xA0000000, 0x20000000, 0 );

/* BIOS library type, same setting is used by IPC as well */
BIOS.libType = BIOS.LibType_Custom;
var SourceDir = xdc.useModule('xdc.cfg.SourceDir');
SourceDir.verbose = 3;

/* Stack size when NULL is passed as stack during TSK create */
Task.defaultStackSize = 0x4000;
/* ISR/SWI stack */
Program.stack = 0x4000;
/* Heap used when creating semaphore's, TSK's or malloc() ... */
Program.heap = 0x15000;

Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;

/*
* Create and install logger for the whole system
*/
var loggerBufParams = new LoggerBuf.Params();
loggerBufParams.numEntries = 32;
var logger0 = LoggerBuf.create(loggerBufParams);
Defaults.common$.logger = logger0;
Main.common$.diags_INFO = Diags.ALWAYS_ON;

System.SupportProxy = SysStd;
/* ================ Driver configuration ================ */

/* Load the OSAL package */
var osType = "tirtos";
var socType = "am572x";
var Osal = xdc.loadPackage('ti.osal');
Osal.Settings.osType = osType;
Osal.Settings.socType = socType;

/*use CSL package*/
var socType = "am572x";
var Csl = xdc.loadPackage('ti.csl');
Csl.Settings.deviceType = socType;

/* Load Profiling package */
var Utils = xdc.loadPackage('ti.utils.profiling');
/* Load the gpio package */
var Gpio = xdc.loadPackage('ti.drv.gpio');
Gpio.Settings.enableProfiling = true;
var Uart = xdc.loadPackage('ti.drv.uart');
var I2c = xdc.loadPackage('ti.drv.i2c');
I2c.Settings.socType = socType;

/* Load the board package */
var Board = xdc.loadPackage('ti.board');
Board.Settings.boardName = "evmAM572x";

var task0Params = new Task.Params();
task0Params.instance.name = "video_task";
Program.global.video_task = Task.create("&videoTaskFxn", task0Params);

Program.sectMap[".bss:extMemNonCache:vpdma"] = "APP_UNCACHED_DATA_BLK3_MEM";
Program.sectMap[".bss:frameBuffer"] = new Program.SectionSpec();
Program.sectMap[".bss:frameBuffer"].loadSegment = "APP_CACHED_DATA_BLK1_MEM";
Program.sectMap[".bss:frameBuffer"].type = "NOLOAD";
Program.sectMap[".bss:tilerBuffer"] = new Program.SectionSpec();
Program.sectMap[".bss:tilerBuffer"].loadSegment = "APP_CACHED_DATA_BLK2_MEM";
Program.sectMap[".bss:tilerBuffer"].type = "NOLOAD";
Program.sectMap[".bss:taskStackSection"] = new Program.SectionSpec();
Program.sectMap[".bss:taskStackSection"].loadSegment = "APP_CACHED_DATA_MEM";
Program.sectMap[".plt"] = "APP_CODE_MEM";
/* Board data and code sections need to go into OCMC when board is supported */
Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";
Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";

/*
* Enable Event Groups here and registering of ISR for specific GEM INTC is done
* using EventCombiner_dispatchPlug() APIs
*/

Ecm.eventGroupHwiNum[0] = 4;
Ecm.eventGroupHwiNum[1] = 5;
Ecm.eventGroupHwiNum[2] = 6;
Ecm.eventGroupHwiNum[3] = 7;
Clock.tickSource = Clock.TickSource_TIMER;

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

In addition, I boot A15 via JTAG with a GEL file: ccs_base\emulation\boards\am572x\gel\gpevm_am572x.gel and download C66 program via JTAG.

CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: IVA DPLL already locked, now unlocking...
CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: ABE DPLL OPP is already locked, now unlocking....
CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GMAC DPLL already locked, now unlocking....
CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GPU DPLL already locked, now unlocking...
CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: DSP DPLL already locked, now unlocking....
CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: PCIE_REF DPLL already locked, now unlocking....
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: DDR DPLL already locked, now unlocking....
CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output: as per HW leveling output
CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output: PHY_STATUSx registers
CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

It also caused the system stuck (in debugger -it's infinite idle loop).

When calling function Task_sleep() from any task, it caused stuck also.

Regards, Andrei

0 Andrei Kolganov over 6 years ago in reply to Andrei Kolganov

Intellectual 275 points

Moreover I created new test project.

In test project I used my BIOS .cfg file. In this case Task_sleep works. But after I selected my custom platform instead default platform system was stucked on Task_sleep().

And corresponding part of .cfg file:

Program.sectMap[".bss:extMemNonCache:vpdma"] = "APP_UNCACHED_DATA_BLK3_MEM";

Program.sectMap[".bss:frameBuffer"] = new Program.SectionSpec();

Program.sectMap[".bss:frameBuffer"].loadSegment = "APP_CACHED_DATA_BLK1_MEM";

Program.sectMap[".bss:frameBuffer"].type = "NOLOAD";

Program.sectMap[".bss:tilerBuffer"] = new Program.SectionSpec();

Program.sectMap[".bss:tilerBuffer"].loadSegment = "APP_CACHED_DATA_BLK2_MEM";

Program.sectMap[".bss:tilerBuffer"].type = "NOLOAD";

Program.sectMap[".bss:taskStackSection"] = new Program.SectionSpec();

Program.sectMap[".bss:taskStackSection"].loadSegment = "APP_CACHED_DATA_MEM";

Program.sectMap[".plt"] = "APP_CODE_MEM";

/* Board data and code sections need to go into OCMC when board is supported */

Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";

Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";

My custom board was created based on .cmd file of baremetal version which works fine.

-stack 0x800 /* SOFTWARE STACK SIZE */

-heap 0x800 /* HEAP AREA SIZE */

/* SPECIFY THE SYSTEM MEMORY MAP */

MEMORY

{

L2_ROM : org = 0x0, len = 0x4000

L2_RAM : org = 0x20000000, len = 0x10000

OCMC_RAM1 : org = 0x40300000, len = 0x80000

OCMC_RAM2 : org = 0x40400000, len = 0x100000

OCMC_RAM3 : org = 0x40500000, len = 0x100000

RST_START : org = 0x00800000 len = 0x0300

IRAM_MEM: org = 0x00800300 len = 0x7c00

APP_CODE_MEM : org = 0x80001000, len = 0x1ff000

// The below memory section is reserved for memory alloc

APP_CACHED_DATA_MALLOC_MEM : org = 0x80200000, len = 0x4000000

APP_CACHED_DATA_MEM : org = 0x84200000, len = 0x8000000

APP_UNCACHED_DATA_BLK3_MEM : org = 0xa4000000, len = 0x200000

APP_CACHED_DATA_BLK1_MEM : org = 0x8C200000, len = 0xFE00000

APP_CACHED_DATA_BLK2_MEM : org = 0x9C000000, len = 0x8000000

}

/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */

SECTIONS

{

.bss:mallocSection : load > APP_CACHED_DATA_MALLOC_MEM, type = NOLOAD

.bss:extMemNonCache:vpdma: load > APP_UNCACHED_DATA_BLK3_MEM

.bss:frameBuffer: load > APP_CACHED_DATA_BLK1_MEM, type = NOLOAD

.bss:tilerBuffer: load > APP_CACHED_DATA_BLK2_MEM, type = NOLOAD

.text: load >> APP_CODE_MEM

.csl_vect : load > RST_START

.vects : load > IRAM_MEM

.l2_int : load > IRAM_MEM

.stack: load > APP_CACHED_DATA_MEM

GROUP: load > APP_CACHED_DATA_MEM

{

.bss:

.neardata:

.rodata:

}

.binit: load > APP_CODE_MEM

.cinit: load > APP_CODE_MEM

.init_array: load > APP_CODE_MEM

.const: load >> APP_CODE_MEM

.data: load >> APP_CACHED_DATA_MEM

.fardata: load >> APP_CACHED_DATA_MEM

.switch: load >> APP_CACHED_DATA_MEM

.sysmem: load > APP_CACHED_DATA_MEM

.far: load >> APP_CACHED_DATA_MEM

.args: load > APP_CACHED_DATA_MEM align = 0x4, fill = 0 {_argsize = 0x0; }

.cio: load >> APP_CACHED_DATA_MEM

.bootVecs: type = DSECT

.resetVecs: load > 0x400

.vecs: load > 0x400, type = DSECT

.plt: load > APP_CODE_MEM

}

Regards, Andrei

0 Andrei Kolganov over 6 years ago in reply to Andrei Kolganov

Intellectual 275 points

The solution of the problem was found:

I created the similar platform but the diference is that I selected as a base chip DRA7XX instead of TMS320C6678. After the video capture began.

Thanks a lot for your help, Eric!

Kind regards, Andrei

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