Tool/software: Code Composer Studio
Hello,
I want to send and receive Direct I/O packets between DSP (C6678) and xilinx FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.
Problem 1:
I studied SRIO_Loopback_evmc6678_C66BiosTestProject example project of SRIO.
In this example, 10 iterations of NWRITE_R packets are send via test_dioSockets() function as follow.
/* Send the DIO Information. */
if (Srio_sockSend (srioSocket, srcDataBuffer, SIZE_DIO_PACKET, (Srio_SockAddrInfo*)&to) < 0)
{
System_printf ("Debug(Core %d): DIO Socket Test Failed\n", coreNum);
return -1;
}
/* Loop around till the transfer is complete. */
while (1)
{
/* Get the completion code. */
if (Srio_getSockOpt(srioSocket, Srio_Opt_DIO_SOCK_COMP_CODE, &compCode, sizeof(uint8_t)) < 0)
{
System_printf ("Error: Unable to get the completion code\n");
return -1;
}
/* Was the transfer complete? */
if (compCode != 0xFF)
break;
}
As shown in this code, the next NWRITE_R packet is sent when completion code of previous NWRITE_R packet is equal to 0. It means that sending of the previous NWRITE_R packet was completed.
Also in this situation, I think that when completion code of previous NWRITE_R packet is equal to 0, it means that the response packet related to NWRITE_R was received.
My first question is:
In the above example, since the next NWRITE_R packet waits until completion of previous NWRITE_R packet (receiving response packet related to previous NWRITE_R), it is not possible to send new NWRITE_R packets. Therefore, it is not possible to achieve the maximum throughput. Is there any way to send DIO packets (such as NWRITE_R) continuously to achieve the maximum throughput?
Problem 2:
As I said, I want to send and receive Direct I/O packets between DSP (C6678) and xilinx FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.
I studied SRIO_TputBenchmarking_evmc6678_C66TestProject example project of SRIO.
Also, I studied Throughput Performance Guide for C66x KeyStone Devices as well as KeyStone Architecture Serial Rapid IO (SRIO) documents.
In KeyStone Architecture Serial Rapid IO (SRIO) document, it was written that:
Also in the example project, the payload size is considered 8 to 8192 bytes.
My second question is:
The maximum payload size is 256 bytes on FPGA side. But on dsp side, it is possible to consider more than 256 bytes (because of packet segmentation).
In this situation, when I send one NWRITE_R packet with 512 bytes payload size from dsp side, I will receive two different NWRITE_R packets with 256 bytes payload size on FPGA? And I should make and send two separate NWRITE_R response packets from FPGA side to dsp side?
Best Regards,
Mohammad
