TDA3MA: EMIF configuration for DDR3 memory

Milan Bajza

Part Number: TDA3MA

Hi all,

I want to configure the EMIF for the IS46TR16640BL DDR3 memory with the EMIF Tool Revision 2.0.2.

http://www.issi.com/WW/pdf/43-46TR16640B-81280BL.pdf

These are my basic settings:

1A) System application details:
1A) System application details:
	Detail	Description	Value	Units
	1	Company / Board Name / Revision (Ex: TI_EVM_revC)	TDA3_IS46TR16640BL	-
	2	TI SOC Part Number	TDA3x_ABF	-
	3	SYS_CLK1 Frequency	20	MHz
	4	Required EMIF Interfaces	1	-
	5	DDR Memory Type	DDR3/L	-
	6	DDR Memory Frequency	532	MHz
	7	DDR Data Bus Width Per EMIF	32	Bits
	8	Leveling Technique: "S/W" or "H/W"	H/W	-
	9	Max DRAM Operating Temperature	<= 105	°C
	10	Enable ECC (May not apply to all EMIFs)	Yes	-
	11	ECC Region 1: System Start Address	80000000	Enabled	NOTE: Values entered into details 11 - 14 must be a hexadecimal value between "80000000" and "FFFFFFFF". Set start and end address to equal values to disable region.
	12	ECC Region 1: System End Address	8FFFFFFF	Enabled
	13	ECC Region 2: System Start Address	80000000	Disabled
	14	ECC Region 2: System End Address	80000000	Disabled

1B) DDR memory specifications:
1B) DDR memory specifications:
	Detail	Description	Value	Units	NOTE: Detail 18 is only used to determine the "JEDEC" values defined in worksheet "Step3-DDRTimings". Detail 18 does not correspond to the actual CAS latency programmed to the EMIF.
	15	Speed Bin: Data Rate	1066	MHz
	16	Density	1	Gb
	17	Width	16	Bits
	18	Speed Bin: CAS Latency @ 1066 MHz data rate	7	ntCK

1C) DDR memory I/O settings (termination / output driver impedance):

	Detail	Description	Value	Units	TI EVM Values**
	19	ODT / Rtt_Nom	RZQ/4	Ohms	RZQ/4
	20	Dynamic ODT / Rtt_Wr	Disabled	Ohms	Disabled
	21	Output Driver Impedance	RZQ/7	Ohms	RZQ/7


1D) EMIF controller I/O settings (termination / output driver impedance / and slew rate):

	Detail	Description	Value	Units	TI EVM Values**
	22	ODT	60	Ohms	60
	23	Slew Rate: Addr/Ctrl/Clk	Fastest: SR[2:0] = 0b000	-	Fastest: SR[2:0] = 0b000
	24	Slew Rate: Data/Strobe	SR[2:0] = 0b010	-	SR[2:0] = 0b010
	25	Output Driver Impedance: Addr/Ctrl/Clk	40	Ohms	40
	26	Output Driver Impedance: Data/Strobe	48	Ohms	48

Q1:
I want set the refresh interval for max temperature range of -40°C to +105°C. tREFI is defined to 3.9µs and tRAS is 9*tREFI.

tRAS (max)	Active to Precharge command period (Max Value)		35100	8	tREFI intervals	8
tREFI	Average periodic refresh interval		3900	2074	tCK	1037

But why the recomanded value is 1037 for tREFI as EMIF value?

Q2:
How much affects increasing the refresh intervall the memory bandwith. Is there a performance test?

Q3:
I am not sure if it's relevant to enable dynamic ODT on our custum HW design, cause it is not recomanded for TDA3-EVM. Is the unused dynamic ODT compensated by HW-Leveling?

Q4
Changing e,g, no "26 Output Driver Impedance: Data/Strobe" has no effect on the generated registers. Why? I could not find the apropriate register in the TRM.

Best regards,
Milan

over 6 years ago

0 Kevin S over 6 years ago

TI__Mastermind 38360 points

Hi,

Q1) Some memories may require a slightly faster refresh rate above 95C. If the memory used in your system only requires 3.9 us, then you can ignore the yellow marking.

Q2) Will follow-up on this question to see if we can provide more information.

Q3) Will follow-up on this question to see if we can provide more information.

Q4) This will impact registers at the SOC level. On the "Register Values (U-Boot)" tab, it will impact the settings under the "ctrl_ioregs" structure.

Best regards,
Kevin

0 Milan Bajza over 6 years ago in reply to Kevin S

Expert 1396 points

Hi Kevin,

thanks for your answers.

Q4) This will impact registers at the SOC level. On the "Register Values (U-Boot)" tab, it will impact the settings under the "ctrl_ioregs" structure.
--> There is no change in "ctrl_ioregs". The change is in EMIF_SDRAM_CONFIG. But the dynamic ODT is not supported, according to TRM. Is it true?

I have an additional question:

Q5) What is the depenency between "21 Output driver impedance" and "25/26 Output drive impedance"? RZQ/7 is 34 Ohm and why is 25/26 recomanded to 40/48 Ohm?

Beste regards,
Milan

0 Kevin S over 6 years ago in reply to Milan Bajza

TI__Mastermind 38360 points

Hi Milan,

Q4) The previous response was in regards to "Changing e,g, no "26 Output Driver Impedance: Data/Strobe" has no effect on the generated registers", which is a controller IO setting and impacts the "ctrl_ioregs" structure. The output driver impedance of the controller is not defined by EMIF_SDRAM_CONFIG.

Q5) Detail 21 assigns the drive impedance of the DDR3 memory for READs. Details 25/26 assign the drive impedance of the SOC DDR controller for WRITEs.

Best regards,
Kevin

0 Milan Bajza over 6 years ago in reply to Kevin S

Expert 1396 points

Hi Kevin

--> Sorry, I confused it

Q5) Detail 21 assigns the drive impedance of the DDR3 memory for READs. Details 25/26 assign the drive impedance of the SOC DDR controller for WRITEs.
--> Ok, I was not aware that a different impedance had to be set for each direction.

Best regards,
Milan

0 Milan Bajza over 6 years ago in reply to Milan Bajza

Expert 1396 points

Hi Kevin,

Is there any news on the questions Q2 and Q3?

Q1) I am unsure about DDR3 refresh. You wrote that I can use the value 2074 (yellow marked) as refresh rate for 105°C. The registers value generated by the EMIF-Tool are:

SDRAM_REF_CTRL = 0x1000081AU;
SDRAM_REF_CTRL_INIT = 0x100040F1U;

In this case the ASR is enabled. So does it mean that the value 0x81A of the refresh register is not used anymore? Is it correct that the DDR3 do the refresh internally without the intervention of EMIF? And what about SRT? Is the bandwith changed dynamically, if the refresh rate is switching? Do
Do you have a recomandation for stable DDR3 access in extended temperature range up to 105°C and constant bandwith?

Best regards,
Milan

0 Kevin S over 6 years ago in reply to Milan Bajza

TI__Mastermind 38360 points

Hi Milan,

ASR and SRT are features of the memory to allow the memory to refresh its own contents when the SOC / controller is powered down. This allows the SOC / controller to go into a low power state and preserve the memory contents to prevent the need to perform a full re-boot. These settings do not apply for normal operation of the SOC / DDR memory.

Q2) I was not able to find any data we could provide that illustrates the impact of the memory bandwidth due to the refresh rate. There is a performance application note at the link below, but I did not see results based on the DDR refresh rate.

www.ti.com/.../sprac21

Q3) Dynamic ODT is not supported on this device. You should keep this disabled.

Best regards,
Kevin

0 Milan Bajza over 6 years ago in reply to Kevin S

Expert 1396 points

Hi Kevin,

thank you for you fast reply.

"ASR and SRT are features of the memory to allow the memory to refresh its own contents when the SOC / controller is powered down. This allows the SOC / controller to go into a low power state and preserve the memory contents to prevent the need to perform a full re-boot. These settings do not apply for normal operation of the SOC / DDR memory."

Currently we are not planing a power down feature.
If ASR and SRT do not apply for normal operation of SOC/DDR memory, why EMIF-Tool enables the ASR-Mode?
So I have to disable ASR and use following value: SDRAM_REF_CTRL = 0x0000081AU for 3,9µs refresh rate controlled by the EMIF, correct?

Best regards,
Milan

0 Kevin S over 6 years ago in reply to Milan Bajza

TI__Mastermind 38360 points

Hi Milan,

If low power modes are not enabled from the controller, then the DRAM should not go into self-refresh mode. If the DRAM does not go into self-refresh mode, then the ASR bit should be a don't care (i.e, there should not be a difference if ASR is '1' or '0' for normal operation). During normal operation, the controller will still send a refresh command to the memory with a set interval determined by the REFRESH_RATE parameter.

Yes, a REFRESH_RATE of 0x81A should correspond to the controller sending a refresh command every 3.9 us with a DDR clock frequency of 532 MHz.

Best regards,
Kevin

0 Kevin S over 6 years ago in reply to Kevin S

TI__Mastermind 38360 points

Hi,

This thread will be closed due to inactivity. If additional questions exist, please let us know.

Thanks,
Kevin

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TDA3MA: EMIF configuration for DDR3 memory