Compiler/TDA2PXEVM: ARM cycle counter

Thanks rishabh, i got that file. But i am building my code using linaro compiler & not as a part of PROCESSOR_SDK. so if i include that header & source asm file also then my build is getting failed. Can you please guide me in this

Regards

Surbhi

Hi Surbhi,

What is the build error you are getting?

Regards,

Rishabh

Hi rishabh,

this is error which i am getting during the build, the out file is not generated.

(.text+0x2ac8): undefined reference to `ARM_CCNT_Enable'
(.text+0x2aec): undefined reference to `ARM_CCNT_Read'
(.text+0x2b00): undefined reference to `ARM_CCNT_Read'
(.text+0x2c34): undefined reference to `ARM_CCNT_Read'
(.text+0x2c48): undefined reference to `ARM_CCNT_Read'
collect2: error: ld returned 1 exit status
Makefile:115: recipe for target 'bin' failed
make: *** [bin] Error 1

Regrads

Surbhi

Hi rishabh,

thank you for the inputs . I am able to link that .o file but it again throws the same error as:

"illegal Instruction". while debug i find that error is coming during "mrc p15, #0, r0, c9, c12, #0", as I am on shortage on time. I have read about a method to invoke the timer registers from the same asm method but by writing a linux kernel, which will enable the user mode. so that this all registers can be accessible. Can you tell me this is the right method to do so? i am sharing the link below:

stackoverflow.com/.../how-to-measure-program-execution-time-in-arm-cortex-a8-processor

Regards

Surbhi

that i get it. But what is ,it telling about this user mode & kernel mode? That i am not able to get it. can you please tell me about this from the link :

qouted--> "@vikramtheone, The first two lines must be executed from kernel mode. They enable user-mode access to the CCNT (and related) registers. There is no way around this. The easiest way is in my opinion to write a super short kernel module that does this. Compiling these modules need the kernel-headers of the kernel you're running on your board".

Regards

Surbhi

as suggested in that link for that error:"Illegal Instruction", i understand that i had to switch to user mode to access this timer registers. If i an wrong please correct. If not the case then, A-15 core is in supervisor mode as you said, then this asm code should not throw that error, isn't it?

Regards

Surbhi

Hi Surbhi,

You don't need to switch to user mode to access timer registers.

Can you provide details on the software you are running before trying to read timer.

Maybe this particular software is setting ARM to user mode.

Can you try to run below code before executing the code to read counter:

/* enable user-mode access to the performance counter*/
  asm ("MCR p15, 0, %0, C9, C14, 0\n\t" :: "r"(1)); 

  /* disable counter overflow interrupts (just in case)*/
  asm ("MCR p15, 0, %0, C9, C14, 2\n\t" :: "r"(0x8000000f));

In case this doesn't work please share your code as a txt file attachment.

Regards,

Rishabh

the code which is shared in that link, i tried the same code in CCS with compiler version:GNU V5.3.1(Linaro). It gets build properly but when i load thta .out file on board & try to run it gives me the same error. I debugged the code & it throws the error at the 1st line only of main where this inline instruction is there:

/* enable user-mode access to the performance counter*/
  asm ("MCR p15, 0, %0, C9, C14, 0\n\t" :: "r"(1)); 

  /* disable counter overflow interrupts (just in case)*/
  asm ("MCR p15, 0, %0, C9, C14, 2\n\t" :: "r"(0x8000000f));


Regards
Surbhi

Hi rishabh,

Using gdb i checked the CPSR register, its value is  "0x60080010".

1. So which mode is in it?

2. Is it specific to change the mode to make that instruction work?

Regards

Surbhi

hi rishabh,

Can you please tell me how to change this bit & where exactly in the previous code:

    /* enable user-mode access to the performance counter*/
asm ("MCR p15, 0, %0, C9, C14, 0\n\t" :: "r"(1));

/* disable counter overflow interrupts (just in case)*/
asm ("MCR p15, 0, %0, C9, C14, 2\n\t" :: "r"(0x8000000f));

Regards

Surbhi

Hi rishabh,

I am not able to change the mode bits of CPSR, gone through arm info-center & other sites also. I used the "SWI" instruction, as it was suggested. If i do exception, the mode will be changed automatically but I  debugged my code,except mode bit other bits gets changed.

--> not getting how to generate a software interrupt in my code.So that when i use SWI instruction to switch to the interrupt, mode bit of CPSR should get changed.

--> There is any other profiling method that can be used for this function profiling as it is there for DSP & EVE  i.e _tsc.

Regards

Surbhi

Hi rishabh,

i don't know how to change the CPSR register value through CCS. can we debug a code through CCS?

I have only tried using code, which i am building it on CCS. The CCS project which i am creating on CCS has its own starup_ARMCA15.S file where the mode is set to USER mode. I tried modifying that file but nothing is getting reflected on CPSR mode bits.

Regards

Surbhi

Hi rishabh,

I am able to change the register value, i.e under Supervisor_Registers , M bit value. I have also checked under the   Core Registers, M bit value, it is been already set to supervised mode.
I am unable to load any .out file on a-15 core. So, how could i verify the changes is getting reflected or not?

Regards

Surbhi

Hi rishabh,

I tried loading the .out file on  CortexA15_0/CortexA15_1, i get this error:

CortexA15_1: File Loader: Verification failed: Values at address 0x00010134 do not match Please verify target memory and memory map.
CortexA15_1: GEL: File: workspace_v6_2/dummy/Debug/dummy.out: a data verification error occurred, file load failed.
CortexA15_1: Unable to terminate memory download: NULL buffer pointer at 0x3aa4 (Emulation package 8.0.803.0)

how to solve this?

Regards

Surbhi

Hi rishabh,

sorry for late response, i get the test code with register changes done & i am able to change the mode bit through register window.


Regards

Surbhi